hsp50210 Intersil Corporation, hsp50210 Datasheet - Page 29

• Manufacturer Part Number: hsp50210
• Description: Digital Costas Loop
• Manufacturer: Intersil Corporation

NOTE: These processor signals are meant to be representative. The actual shape of the waveforms will be set by the microprocessor used. Verify
that the processor waveforms meet the parameters in the Waveforms Section of this data sheet to ensure proper operation. The Processor wave-
forms are not required to be synchronous to CLK. They are shown that way to clarify the illustration.
10
1
2
3
4
5
6
7
8
9
BIT
7
6
5
4
Load the Write Address Register with 24
Load the Read Address Register with 3
Read Internal Status Register to monitor SR-7 to determine when the Lock Detector is stopped and ready to be read.
SR-7 goes high, indicating the Lock Detector integration cycle is complete, and ready to be read.
Read Internal Status Register and find SR-7 = 1; the Lock Detector is ready to be read.
Change Read address to (3; 2; 1; 0) for (Phase Error MSW; PE LSW; False Lock MSW; FL LSW) read.
End of Internal Status Valid Data.
Assert RD to Read Lock Detector Status
Load The Write Address Register with 30
Load the Write Address Register with 25
counter in the lock detector. The verify counter is not reset and will resume at the stopped value when the lock detector is restarted.
machine mode).
SR-7
A0-2
C0-7
CLK
WR
RD
Lock Detector Stopped and Ready for Reading
(State Machine Control Mode).
0 = Lock Detector not stopped.
1 = Lock Detector stopped, ready for read.
Lock Detector Stopped and Ready for Reading
(Microprocessor Control Mode).
0 = Lock Detector not stopped.
1 = Lock Detector stopped, ready for read.
Carrier Loop Filter Lag Accumulator Load Complete. This bit
is used to determine when a 32-bit load of Carrier Lag Accu-
mulator is complete. The accumulator load is initialized by
loading the Write Address Register with 13 (decimal) as de-
scribed in Table 27.
0 = Load not complete.
1 = Load complete.
Symbol Tracking Loop Filter Lag Accumulator Load
Complete. This bit is used to determine when a 32-bit load
of Symbol Track Lag Accumulator is complete. The
accumulator load is initialized by loading the Write Address
Register with 19 (decimal) as described in Table 33.
0 = Load not complete.
1 = Load complete.
AT END OF
HALT LD
CYCLE
24
FIGURE 23. PROCESSOR MONITORING INTERNAL STATUS/READING LOCK DETECTOR
4
1
BIT DESCRIPTION
3-29
FOR READING
ENABLE
LD REG.
5
3
2
SR7=0
TABLE 13. INTERNAL STATUS REGISTER (SR7-0) BIT MAP
dec
dec
dec
dec
3
STATUS READS
to enable the Lock Detector Phase Error Accumulator for reading.
to halt the Lock Detector after the current integration cycle. This disables the reload of the integration
to restart the Lock Detector.
4
to initialize Lock Detector Accumulators and Reset the Integration counters. (Not needed for state
INTERNAL
4
5
SR7=1
6
7
HSP50210
8
3
PE
MSW
LOCK DETECTION STATUS READS
6
BIT
2
8
PE
3
2
1
0
LSW
Lock. Carrier Lock state achieved by Lock Detector.
0 = Not locked.
1 = Locked.
Acquisition/Track. Indicates whether the Lock Detector is in
acquisition or tracking mode.
0 = Tracking Mode.
1 = Acquisition Mode.
Reserved.
Frequency Sweep Direction, defined for upper sideband sig-
nals.
0 = UP.
1 = DOWN.
6
8
1
FL
MSW
BIT DESCRIPTION (Continued)
6
0
8
FL
LSW
9
DETECTOR
RESET
LOCK
30
10
4
DETECTOR
RESTART
LOCK
25