hsp50210 Intersil Corporation, hsp50210 Datasheet - Page 44

• Manufacturer Part Number: hsp50210
• Description: Digital Costas Loop
• Manufacturer: Intersil Corporation

OUTPUT
OUTPUT
SELECT
SELECT
POSITION
0000
0001
0010
0011
0100
0101
0110
0111
1000
0000
0001
0010
0011
0100
0101
0110
0111
1000
BIT POSITION
BIT
N/A
STATUS2
STATUS6
STATUS2
STATUS2
STATUS2
STATUS2
LKACC2
Iend3
NCOCOS9 NCOCOS8 NCOCOS7 NCOCOS6 NCOCOS5 NCOCOS4 NCOCOS3 NCOCOS2 NCOCOS1 NCOCOS0
ISOFT2
ISOFT2
ISOFT2
ISOFT2
ISOFT2
ISOFT2
ISOFT2
ISOFT2
RSRVD7
BOUT 9
AOUT 9
Load Output Holding
Register for
Microprocessor Read
FUNCTION
STATUS1
STATUS0
STATUS1
STATUS1
STATUS1
STATUS1
LKACC1
Iend2
FUNCTION
ISOFT1
QSOFT2
ISOFT1
ISOFT1
ISOFT1
ISOFT1
ISOFT1
ISOFT1
RSRVD6
TABLE 42. OUTPUT SELECTOR CONFIGURATION CONTROL REGISTER (Continued)
BOUT 8
AOUT 8
3-44
TABLE 43. UPDATE READ REGISTER CONFIGURATION CONTROL REGISTER
STATUS0
PHASE7
STATUS0
STATUS0
STATUS0
STATUS0
LKACC0
Iend1
ISOFT0
MAG7
ISOFT0
ISOFT0
ISOFT0
ISOFT0
ISOFT0
ISOFT0
RSRVD5
BOUT 7
FREQERR(7:1), GAINERR(7:1), BITPHERR(7:1), and CARPHERR(7:1)
These signals are useful in applications that need these signals output at the symbol rate and available
for hardwiring, rather than at the processor access rate. Configurations that use the DCL as a stand alone
demodulator and matched filter are examples of such applications.
LKACC(6:0) and LKCNT(6:0)
These signals are provided for applications which require a lock detection interface that is not processor
dependent. These signals are also useful in fault detection in BIT/BITE applications.
NCOCOS(9:0)
This signal is provided for use when the DCL is configured as a stand alone Loop Filter and NCO. This
signal can be useful in fault detection in BIT/BITE applications.
Loading the Address Register with this destination address samples the contents of the Carrier Loop
Filter Lag Accumulator, Symbol Tracking Loop Filter Lag Accumulator, and the AGC Accumulator. The
sampled accumulator values are loaded into the output holding registers for reading via the
Microprocessor Interface. Allow 6 CLKs until the output holding register is stable for reading.
AOUT 7
AGC7
PHASE6
FE7
GE7
TE7
CARPE7
LKCNT6
Qend7
TABLE 42A. AOUT BIT DEFINITIONS
QSOFT2
MAG6
QSOFT2
QSOFT2
QSOFT2
QSOFT2
QSOFT2
QSOFT2
RSRVD4
TABLE 42B. BOUT BIT DEFINITION
BOUT 6
AOUT 6
DESTINATION ADDRESS = 28
DESTINATION ADDRESS = 29
HSP50210
AGC6
PHASE5
FE6
GE6
TE6
CARPE6
LKCNT5
Qend6
QSOFT1
MAG5
QSOFT1
QSOFT1
QSOFT1
QSOFT1
QSOFT1
QSOFT1
RSRVD3
BOUT 5
AOUT 5
AGC5
PHASE4
FE5
GE5
TE5
CARPE5
LKCNT4
Qend5
BOUT 4
QSOFT0
MAG4
QSOFT0
QSOFT0
QSOFT0
QSOFT0
QSOFT0
QSOFT0
RSRVD2
AOUT 4
DESCRIPTION
DESCRIPTION
AGC4
PHASE3
FE4
GE4
TE4
CARPE4
LKCNT3
Qend4
BOUT 3
STATUS6
MAG3
STATUS6
STATUS6
STATUS6
STATUS6
LKACC6
Iend7
RSRVD1
AOUT 3
ACG3
PHASE2
FE3
GE3
TE3
CARPE3
LKCNT2
Qend3
STATUS5
MAG2
STATUS5
STATUS5
STATUS5
STATUS5
LKACC5
Iend6
RSRVD0
BOUT 2
AOUT 2
AGC2
PHASE1
FE2
GE2
TE2
CARPE2
LKCNT1
Qend2
STATUS4
MAG1
STATUS4
STATUS4
STATUS4
STATUS4
LKACC4
Iend5
STATUS5
BOUT 1
AOUT 1
AGC1
PHASE0
FE1
GE1
TE1
CARPE1
LKCNT0
Qend1
STATUS3
MAG0
STATUS3
STATUS3
STATUS3
STATUS3
LKACC3
Iend4
STATUS6
BOUT 0
AOUT 0