hsp50210 Intersil Corporation, hsp50210 Datasheet - Page 43

• Manufacturer Part Number: hsp50210
• Description: Digital Costas Loop
• Manufacturer: Intersil Corporation

:
BIT POSITION
31-8
7-4
3-0
Not Used
Reserved
Output Select
FUNCTION
3-43
TABLE 42. OUTPUT SELECTOR CONFIGURATION CONTROL REGISTER
No programming required.
Set to zero for proper operation.
These bits select which input signals are routed to the 20 output pins AOUT9-0 and BOUT9-0. The signal
selections are listed below in Tables 42A and 42B.
Definition of Signal Bus Names:
Data Signal Busses:
ISOFT(2:0) This bus is the I channel soft decision slicer output data, expressed in the data format set
QSOFT(2:0) This bus is the Q channel soft decision slicer output data, expressed in the data format set
IEND(7:1)
QEND(7:1)
Status Signal Parameter Busses:
AGC(7:1) . . . . . This bus is the 7 MSB’s of the AGC Accumulator Register. (MSB = AGC7).
MAG (7:0) . . . . This bus is the 8-bit magnitude output of the Cartesian to Polar converter, in unsigned
PHASE (7:0) . . This bus is the 8-bit phase output of the Cartesian to Polar converter, in unsigned binary
FE(7:1) . . . . . . This bus is the seven MSB’s of the Frequency Error Detector Output Register, in 2’s
GE (7:1) . . . . . This bus is the seven MSB’s of the Gain Error (AGC) Accumulator Register, in 2’s com-
TE (7:1) . . . . . This bus is the seven MSB’s of the Bit Phase Error Detector Output Register, in 2’s com-
CARPE (7:1) . . This bus is the seven MSB’s of the Carrier Phase Error Detector Output Register, in 2’s
LKACC(6:0) . . .This bus is the seven LSB’s of the Phase Error Accumulator Register in the Lock Detector,
LKCNT(6:0) . . This bus is the seven LSB’s of the Integration Counter in the Lock Detector, in one’s
NCOCOS(9:0) . This bus is the 10-bit two’s complement output of the DCL NCO, in 2’s complement for-
Applications for the Various Output Signals:
ISOFT(2:0) and QSOFT(2:0)
These signals provide a simple interface to a FEC decoder. As the most likely to be used output bus, these
signals are included in all but one of the programmable multiplexer output configurations.
IEND(7:1) and QEND(7:1)
These signals are useful when input to a D/A converter and displayed on an oscilloscope in the X-Y plot.
This will yield the constellation signal display with which analog modem designers are familiar.
STATUS(6:0)
These signals can be used in fault detection for use in BIT/BITE applications and are useful during sys-
tem debug.
AGC(7:1)
This signal is useful in monitoring the AGC operation, signal detection and antenna tracking applications.
Other single bit signals are provided for direct use in external AGC.
MAG(7:0) and PHASE(7:0)
These signals are useful in signal detection applications, where presence of a signal is represented by a
particular signal magnitude or phase.
by CW26 bit 7, with one sign bit (ISOFT2) and two soft decision bits.
by CW26 bit 7, with one sign bit (QSOFT2) and two soft decision bits.
This bus is the 7 MSB’s of I end symbol sample into the soft decision slicer, in 2’s comple-
ment format. (MSB = Iend7).
This bus is the 7 MSB’s of Q end symbol sample into the soft decision slicer, in 2’s comple-
ment format. (MSB = Qend7).
DESTINATION ADDRESS = 28
binary format. (MSB = MAG7).
format. (MSB = PHASE7).
complement format. (MSB = FE7).
plement format. (MSB = GE7).
plement format. (MSB = TE7).
complement format. (MSB = PE7).
in unsigned offset binary format. (MSB = LKACC6) If accumulation bits 14-17 = 1, then
bits 7-13 are output as LKACC(6.0). These outputs are zero otherwise.
complement format. (MSB = LKCNT6) If bits 7-9 of the accumulator are zero, then bits
0-6 are output as LKCNT(6-0). These outputs are zero otherwise.
mat. (MSB = NCOCOS7).
HSP50210
DESCRIPTION