hsp50214 Intersil Corporation, hsp50214 Datasheet - Page 25

• Manufacturer Part Number: hsp50214
• Description: Programmable Downconverter
• Manufacturer: Intersil Corporation

†
Cartesian to Polar Converter
The Cartesian to Polar converter computes the magnitude
and phase of the I/Q vector inputs. The I and Q inputs are
16 bits. The converter phase output is 18 bits (truncated)
with the 16 MSB’s routed to the output formatter and all 18
bits routed to the frequency discriminator. The 16-bit output
phase can be interpreted either as two’s complement (-0.5 to
approximately 0.5) or unsigned (0.0 to approximately 1.0),
as shown in Figure 28. The phase conversion gain is 1/2 .
The phase resolution is 16 bits. The 16-bit magnitude is
unsigned binary format with a range from 0 to 2.32. The
magnitude conversion gain is 1.64676. The magnitude reso-
lution is 16 bits. The MSB is always zero.
Table 11 details the phase and magnitude weighting for the
16 bits output from the PDC.
R
T
Controlled via microprocessor interface.
T
X
(REFCLK)
= TOTAL DECIMATION (CIC, HB FILTERS AND FIR)
DATA CLK
TIMING
ACC.
NCO
FIGURE 27A. TIMING ERROR APPLICATION
NCO DIVIDE = 4N
PROGRAMMABLE
PROGRAMMABLE
REFERENCE
DIVIDE = N
CLKIN/R
DIVIDER
P
DIVIDER
FILTER
LOOP
T
†
†
(NCO DIVIDE)/2
12
4
EN
TO T
(MODULATOR)
X
BLOCK
-
+
†
TE(15:0)
HSP50214
25
The magnitude and phase computation requires 17 clocks
for full precision. At the end of the 17 clocks, the magnitude
and phase are latched into a register to be held for the next
stage, either the Output Formatter or frequency discrimina-
tor. If a new input sample arrives before the end of the 17
cycles, the results of the computations up until that time, are
latched. This latching means that an increase in speed
causes only a decrease in resolution. Table 12 details the
exact resolution that can be obtained with a fixed number of
clock cycles up to the required 17. The input magnitude and
phase errors induced by normal SNR values will almost
always be worse than the Cartesian to Polar conversion.
FIGURE 28. PHASE BIT MAPPING OF COORDINATE
8000
7fff
15 (MSB)
0 (LSB)
BIT
14
13
12
11
10
9
8
7
6
5
4
3
2
1
4000
TABLE 11. MAG/PHASE BIT WEIGHTING
bfff
CONVERTER OUTPUT
+
-
/2
Q
/2
c000
3ff f
I
0000
ffff
0
MAGNITUDE
2
2
Always 0
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
-10
-11
-12
-13
-1
-2
-3
-4
-5
-6
-7
-8
-9
1
0
8000
7fff
4000
180
90
45
22.5
11.25
5.625
2.8125
1.40625
0.703125
0.3515625
0.17578125
0.087890625
0.043945312
0.021972656
0.010986328
0.005483164
bfff
3 /2
/2
PHASE (
Q
c000
3fff
I
0000
ffff
o
0
)