hsp50214 Intersil Corporation, hsp50214 Datasheet - Page 31

• Manufacturer Part Number: hsp50214
• Description: Programmable Downconverter
• Manufacturer: Intersil Corporation

Buffer RAM Output Port
The Buffer RAM parallel output mode utilizes a RAM to store
output data for future retrieval by either the 8-bit microproces-
sor that is configuring the PDC or by a 16-bit baseband pro-
cessing engine (which could also be a microprocessor). Data
is output from the RAM only on request and can be obtained
from either the 8-bit P interface or from a 16-bit interface that
uses the two LSBytes of AOUT and BOUT. The RAM holds up
to eight 80-bit sample sets. Each sample set includes 16 bits
of each I, Q, magnitude, phase, and frequency data. The
RAM samples are mapped as shown in Table 16. The Buffer
RAM controller supports both FIFO and Snapshot modes.
NOTE: I and Q are sample aligned in time. |r| and
SAMPLE
LSB WORD0
RAM
“NORMAL”
“INVERTED”
“NORMAL”
“INVERTED”
SET
0
1
2
3
4
5
6
7
2
aligned in time, but one sample delayed from I or Q. The
frequency sample is delayed in time from I or Q by 1
sample time + 63 tap FIR impulse response. If the FIR is
set to decimate, the FIR output will be repeated every
sample time until a new value appears at the filter output.
(i.e., the frequency samples are clocked out at the I, Q
sample rate regardless of decimation.)
I
I
I
I
I
I
I
I
TABLE 16. RAM DATA STORAGE MAP
1
DATA
0
1
2
3
4
5
6
7
(000)
(15:0)
(15:0)
(15:0)
(15:0)
(15:0)
(15:0)
(15:0)
(15:0)
I
1
1
0
DATA SHIFT MSB FIRST
SERSYNC PRECEDES MSB
15
0
0
Q
Q
Q
Q
Q
Q
Q
Q
DATA
(001)
0
1
2
3
4
5
6
7
(15:0)
(15:0)
(15:0)
(15:0)
(15:0)
(15:0)
(15:0)
(15:0)
Q
SERSYNC FOLLOWS LSB
14
MSB WORD1
|r|
|r|
|r|
|r|
|r|
|r|
|r|
|r|
• • •
DATA
(010)
0
1
2
3
4
5
6
7
(15:0)
(15:0)
(15:0)
(15:0)
(15:0)
(15:0)
(15:0)
(15:0)
|r|
FIGURE 33. VALID SERSYNC CONFIGURATION OPTIONS
2
DATA
0
1
2
3
4
5
6
7
(011)
1
(15:0)
(15:0)
(15:0)
(15:0)
(15:0)
(15:0)
(15:0)
(15:0)
2
2
0
are sample
15
f
f
f
f
f
f
f
f
1
1
LSB WORD1
0
1
2
3
4
5
6
7
DATA
(100)
(15:0)
(15:0)
(15:0)
(15:0)
(15:0)
(15:0)
(15:0)
(15:0)
HSP50214
F
14
MSB WORD2
31
• • •
The FIFO mode allows the processor to service the interface
only when enough samples are present in the RAM. This
mode is provided so that the Processor does not have to
service the PDC every output sample. An interrupt,
INTRRPT, is asserted when the desired number of samples
are available. The PDC can be programmed to assert the
interrupt when up to 7 samples are available. Control Word
21 bit 15 is used to set the Buffer RAM controller to the FIFO
mode, while Control Word 21, bits 12-14 set the number of
RAM samples to be stored (0 to 7) before the interrupt
(INTRRPT) is asserted. Control Word 20 bit 24 determines
whether the RAM output interface is the 8-bit microprocessor
interface or the 16-bit processor interface. In the 16-bit inter-
face the MSByte is sent to AOUT(7:0) while the LSByte is
sent to BOUT(7:0).
The INTRRP output signal goes low for 8 PROCCLK cycles
when the number of samples in the Buffer RAM (depth)
reaches the programmed depth. The depth of the RAM is
calculated using Equation 23. A DSP microprocessor or the
data processing engine can use the INTRRP signal to know
that the RAM is ready to be read.
FIFO Operation via 16-Bit Processor
Interface
Figure 34 shows the conceptual configuration of the 16-bit
cessor read-only microprocessor interface. The SEL(2:0)
lines are the address bus and the OEAL and OEBL lines are
the read lines. The address is decoded as shown in
Table 17.
Use of the 16-bit interface for Buffer RAM output requires
Control Word 20, bit 25, to be set to a logic “0” and Control
Word 20, bit 24, to be set to a logic “1”. Once the Control
D
Processor interface. This interface looks like a 16-bit Pro-
RAM
2
=
ADDR
1
3
3
0
W RITE
15
2
LSB WORD2
2
14
–
MSB WORD3
ADDR
• • •
READ
2
–
1
MOD8
LATE
SERSYNC
MODE
EARLY
SERSYNC
MODE
(EQ. 23)