hsp50214 Intersil Corporation, hsp50214 Datasheet - Page 26

• Manufacturer Part Number: hsp50214
• Description: Programmable Downconverter
• Manufacturer: Intersil Corporation

Frequency Discriminator
The discriminator block delays phase from the Cartesian to
Polar section and subtracts it from the latest sample. This
delay and subtract can be modeled as a programmable
delay comb filter. The output of the filter is d /dt, or fre-
quency. The transfer function of the discriminator is set by
where D is the programmable discriminator delay expressed
in number of sample clock delays. The discriminator output
frequency is then filtered with a programmable FIR filter. The
block diagram of the Frequency Discriminator is shown in
Figure 29.
The range of delay in the discriminator is from 1 to 8 sam-
ples. Modulo 2 subtraction eliminates rollover problems in
the subtraction at 2 . The alias free discriminator frequency
range is given by:
Range
where D is the discriminator delay defined in Equation 21
(1 < D < 8), FSAMP
sample rate and CW is the desired center frequency. When
the phase multiplier is set to a value other than 2
criminator range is reduced proportionally. The phase multi-
plier can be 1, 2, 4 or 8 (2
reduces the range by 2, a multiply of 2
by 4, and a multiply of 2
The FIR filter can be configured with up to 63 symmetric taps
and up to 32 asymmetric taps. In the symmetric mode, the
FIR can be configured for even or odd symmetry, as well as
with an even or odd number of filter taps. Decimation is pro-
vided to allow more processing time for longer (i.e., more
taps) filter structures.
H z
†
Assumes 180
TABLE 12. MAG/PHASE ACCURACY vs CLOCK CYCLES
CLOCKS
=
FREQDISC
10
11
12
13
14
15
16
17
6
7
8
9
1 Z
–
–
D
o
=
MAGNITUDE
= f
CW
ERROR
<0.004
<0.004
<0.004
<0.004
<0.004
<0.004
<0.004
<0.004
<0.004
(% f
S
OUT
0.065
0.016
0.004
.
S
3
)
F
is the Discriminator FIR filter output
reduces the range by 8.
SAMPOUT
0
to 2
ERROR
(DEG.)
0.00175
PHASE
3
0.0035
0.056
0.028
0.014
0.007
). Thus, a multiply of 2
0.45
0.22
0.11
3.5
1.8
0.9
D
+
2
†
1
reduces the range
;
ERROR
PHASE
(% f
0
0.062
0.016
0.008
0.004
0.002
0.001
0.25
0.12
0.03
0.5
, the dis-
2
1
(EQ. 21)
(EQ. 22)
S
HSP50214
)
1
26
†
The discriminator input is 18 bits, and the output is rounded
asymmetrically to 16 bits. The phase into the discriminator
can be multiplied by 2
PSK data modulation. All programmable parameters for the
Frequency Discriminator are set in Control Word 17. Bits 15
and 16 are the phase multiplier which represents the shift
applied to the input phase. For CW, the multiply should equal
2
equal 2
used to enable or disable the discriminator. Bits 11-13 set
the decimation in the programmable FIR filter. Bit 10 sets the
filter symmetry type as either odd or even, bit 9 sets whether
the filter is asymmetric or symmetric, and bits 3-8 set the
number of FIR filter taps. Bits 0-2 set the number of delays in
the frequency discriminator.
Output Section
The output section routes the 7 types of processed signals to
output pins in three basic modes. These basic modes are:
Parallel Direct Output, Serial Direct Output, and the Buffer
RAM Output. The Serial and Parallel Direct Output modes
were designed to output data strobes and “real time” continu-
ous streams of data. The Buffer RAM Output mode outputs
data upon receipt of an asynchronous request from an exter-
nal DSP processor or other baseband processing engine. The
use of the interrupt signal from the Programmable Down Con-
verter in conjunction with the request strobes from the control-
ler ensures that data is transferred only when both the
controller and the Programmable Down Converter are ready.
The Buffer RAM output can be operated in a First In First Out
(FIFO) or SNAPSHOT mode with the data output either via
the 8-bit processor interface or a 16-bit processor interface.
FIGURE 29. FREQUENCY DISCRIMINATOR BLOCK DIAGRAM
0
Controlled via microprocessor interface.
, (00). For BPSK, QPSK, and 8PSK, the multiply should
DISCRIMINATOR DELAY
DISC. FIR DECIMATION
FIR SYMMETRY TYPE
PHASE MULTIPLIER
DISCRIMINATOR EN
FIR COEFFICIENTS
1
, (01); 2
PHASE INPUT
FIR SYMMETRY
FIR TAPS
2
, (10); or 2
0
, 2
†
†
†
†
†
†
†
†
1
, 2
2
3
, or 2
63-TAP
FILTER
, (11); respectively. Bit 14 is
DELAY
-
(1-8)
FIR
+
3
+
(modulo 2 ) to remove
FREQ(15:0)