hsp50214 Intersil Corporation, hsp50214 Datasheet - Page 45

• Manufacturer Part Number: hsp50214
• Description: Programmable Downconverter
• Manufacturer: Intersil Corporation

POSITION
POSITION
31-12
31-17
16-15
13-11
11-4
CONTROL WORD 17: DISCRIMINATOR FILTER CONTROL, DISCRIMINATOR DELAY (SYNCHRONIZED TO PROCCLK)
BIT
BIT
2-0
8-3
2-0
14
10
3
9
Reserved
Phase Multiplier
Discriminator Enable
Discriminator FIR
Decimation
FIR Symmetry Type
FIR Symmetry
Number of FIR Taps
Discriminator Delay
Reserved
Resampler Output
Pulse Delay
Resampler Bypass
Filter Mode Select;
2- HB2 Enabled
1- HB1 Enabled
0- Resampler
Enabled
CONTROL WORD 16: RE-SAMPLING FILTER CONTROL (SYNCHRONIZED TO PROCCLK)
FUNCTION
FUNCTION
NOTE: These bits program the delay between output samples when interpolating. The extra out-
NOTE: If less than 5 is programmed, there will not be sufficient time to fully update the out-
Reserved.
These bits program allow the phase output of the cartesian to polar converter to be multiplied by
1, 2, 4, or 8 (modulo 2 ) to remove phase modulation before the frequency is measured.
00- No Shift on Phase Input to frequency discriminator.
01- Shift Phase Input to frequency discriminator up 1 (one bit), discarding the MSB and zero filling
the LSB.
10- Shift Phase Input to frequency discriminator up 2 (two) bits, discarding the MSB and zero fill-
ing the LSB.
11- Shift Phase Input to frequency discriminator up 3 (three) bits, discarding the MSB and zero
filling the LSB.
0- Disable Discriminator.
1- Enable Discriminator.
The decimation can be programmed from 1 to 8, where 000 = decimate by 8; 001 = decimate by
1; 010 = decimate by 2; 011 = decimate by 3; 100 = decimate by 4; 101 = decimate by 5; 110 =
decimate by 6; and 111 - decimate by 7.
0- Odd Symmetry.
1- Even Symmetry.
0- Symmetric.
1- Asymmetric.
Number of FIR taps from 1 to 63, where 00000 is not valid (00001 = 1 tap, 00010 = 2 taps, etc.
up to 11111 = 63 taps). Bit 8 is the MSB.
where 000 represents 1 delay; 001 represents 2 delays, 010 represents 3 delays, 011 repre-
sents 4 delays, 100 represents 5 delays, 101 represents 6 delays, 110 represents 7 delays, and
111 represents 8 delays. If ddd the decimal representation bits 2-0, then the discriminator a
transfer function H(Z) = 1-Z
Sets the number of delays from 1 to 8 in the discriminator. Set delay ddd to delay minus 1,
Reserved.
0- Re-Sampling Filter Enabled. A valid combination of bits 2-0 must also be selected.
1- Re-Sampling Filter is Bypassed.
000- Not Valid.
001- Resampler Enabled.
010- Halfband 1 Enabled.
011- Resampler and Halfband Filter 1 Enabled.
100- Not Valid.
101- Not Valid.
110- Both Halfband Filters Enabled.
111- Resampler and Both Halfband Filters Enabled.
puts can be delayed from 2 to 255 clocks from the first output. A delay of 2 equals 255
clocks of delay. A delay of 0 or 1 is an invalid mode. When interpolating by 2, one extra
output is generated; when interpolating by 4, 3 extra outputs are generated. Program by
the equation (PROCCLK/f
put buffer. If less than 16 is programmed, the serial output may be preempted. This
means that it won’t finish and if the sync is programmed to follow the data, there
may never be a sync.
HSP50214
45
-(ddd + 1)
OUT
.
) - 1. Bit 11 is the MSB.
DESCRIPTION
DESCRIPTION