ak4562 AKM Semiconductor, Inc., ak4562 Datasheet - Page 12

• Manufacturer Part Number: ak4562
• Description: Low Power 20bit Codec With Pga
• Manufacturer: AKM Semiconductor, Inc.

ASAHI KASEI
n System Clock
The clocks that are required to operate are MCLK (256fs/384fs), LRCK (fs) and BCLK (32fs ). The master clock
(MCLK) should be synchronized with LRCK but the phase is free of care. The frequency of MCLK can be input 256fs or
384fs. When the 384fs is input, the internal master clock is divided into 2/3 automatically.
*fs is sampling frequency.
All external clocks (MCLK, BCLK and LRCK) should always be present whenever ADC and DAC are in operation. If
these clocks are not provided, the AK4562 may draw excess current and it is not possible to operate properly because
utilizes dynamic refreshed internally. If the external clocks are not present, the AK4562 should be in the power-down
mode.
n Audio Data I/F Format
Using SDTO, SDTI, BCLK and LRCK pins are connected to external system. Audio data format has four kinds of mode,
the data format is MSB-first, 2’s compliment. Setting by DIF0-1 bit. The default value is DIF0 = DIF1 = “0”.
MS0031-E-00
LRCK
BCLK(64fs)
SDTO(o)
SDTI(i)
LRCK
BCLK(64fs)
SDTO(o)
SDTI(i)
No.
0
1
2
3
DIF1 bit
0
0
1
1
0
0
19
19:MSB, 0:LSB
SDTO-19:MSB, 0:LSB; SDTI-15:MSB, 0:LSB
19
Don’t Care
1
1
18
18
DIF0 bit
Don’t Care
2
2
0
1
0
1
8
5
12
15
19
7
4
20bit MSB justified
20bit MSB justified
20bit MSB justified
13
Lch Data
16
Lch Data
I
SDTO (ADC)
18
2
15
6
S Compatible
3
14
17
Figure 7. Audio Data Format (No.0)
Figure 8. Audio Data Format (No.1)
Table 1. Audio Data Format
12 11
12 11
0
0
OPERATION OVERVIEW
20
20
21
21
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1
1
20bit LSB justified
16bit LSB justified
24bit LSB justified
31
31
I
2
SDTI (DAC)
S Compatible
0
0
0
0
19 18
19 18
Don’t Care
1
1
Don’t Care
2
2
8
5
12
15
19
Lch: “H”, Rch: “L”
Lch: “H”, Rch: “L”
Lch: “H”, Rch: “L”
Lch: “L”, Rch: “H”
7
4
13
Rch Data
16
Rch Data
18
15
6
3
14
17
LRCK
12 11
12 11
0
0
20
20
21
21
BCLK
1
1
31
31
40fs
32fs
48fs
40fs
[AK4562]
0
0
2000/05
0
0
19
19
1
1