ak4562 AKM Semiconductor, Inc., ak4562 Datasheet - Page 9
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ak4562
Manufacturer Part Number
ak4562
Description
Low Power 20bit Codec With Pga
Manufacturer
AKM Semiconductor, Inc.
Datasheet
1.AK4562.pdf
(29 pages)
ASAHI KASEI
(Ta=-20
Parameter
Control Clock Frequency
Audio Interface Timing
Control Interface Timing (AKM)
Control Interface Timing (SSB)
Reset / Calibration Timing
Note : 14. These cycles are the numbers of LRCK rising from PDN pin rising.
MS0031-E-00
Master Clock (MCLK)
Channel Clock (LRCK)
PDN Pulse Width
PDN “ ” to SDTO
BCLK Period
BCLK Pulse Width Low
BCLK “ ” to LRCK
LRCK Edge to SDTO (MSB)
BCLK “ ” to SDTO
SDTI Hold Time
SDTI Setup Time
CCLK Period
CCLK Pulse Width Low
CDATA Setup Time
CDATA Hold Time
CSN “H” Time
CSN “ ” to CCLK “ ”
CCLK “ ” to CSN “ ”
SCK Period
SCLK Pulse Width Low
SSI Setup Time
SSI Hold Time
70 C; VA, VD=2.2 3.0V, VT=1.8
Pulse Width High
Pulse Width High
Pulse Width High
256fs: Frequency
384fs: Frequency
Pulse Width Low
Pulse Width High
Pulse Width Low
Pulse Width High
Frequency
Duty Cycle
(Note 14)
SWITCHING CHARACTERISTICS
3.0V; C
Symbol
tBLKH
tCCKH
tCLKH
tCLKH
tBLKL
tCCKL
tSCKH
tCLKL
tCLKL
tSCKL
tPWV
tCDH
tCSW
fCLK
fCLK
tBLK
tDLR
tSDH
tCCK
tBLR
tCDS
tCSH
tSCK
tDSS
tSDS
tCSS
tSIH
tPW
tSIS
L
fs
- 9 -
=20pF)
-tBLKH+50
2.048
3.072
312.5
min
130
130
200
150
250
100
100
150
28
28
23
23
45
50
50
80
80
50
50
50
50
50
50
8
11.2896
16.9344
4128
44.1
typ
tBLKL-50
max
12.8
19.2
50
55
80
80
[AK4562]
MHz
MHz
2000/05
kHz
1/fs
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns