ak4537 AKM Semiconductor, Inc., ak4537 Datasheet
ak4537
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ak4537 Summary of contents
Page 1
... ASAHI KASEI 16-Bit The AK4537 targeted at PDA and other low-power, small size applications. It features a 16-bit stereo CODEC with a built-in Microphone-Amplifier, Headphone-Amplifier and Speaker-Amplifier. Input circuits include a Microphone-Amplifier and an ALC (Auto Level Control) circuit. The AK4537 is available in a 52-QFN, utilizing less board space than competitive offerings. ...
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... MIX PMDAC PMMIX MIX DATT DAC SMUTE MIX MIX MIX PMSPK MIX PMBPS PMBPM MIN BEEPL BEEPR BEEPM MOUT2 Figure 1. Block Diagram - 2 - [AK4537] M/S AVSS AVDD CAD0 Audio PDN Interface LRCK BICK SDTO DSP SDTI and uP I2C CSN/CAD1 CCLK/SCL Control Register CDTI/SDA ...
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... ASAHI KASEI „ Ordering Guide AK4537VN 10 AKD4537 Evaluation board for AK4537 „ Pin Layout MICOUTL MICOUTR 2 EXT/MICR 3 MPE 4 MPI 5 INT/MICL 6 VCOM 7 AVSS 8 AVDD 9 PVDD 10 PVSS 11 VCOC MS0202-E-04 +70 C 52pin QFN (0.4mm pitch AK4537VN Top View ...
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... TST4 TST5 AIN NC MOUT) is added LOUT/ROUT, HP-Amp, SPK-Amp) is added. MOUT ATT Select) is added. LOUT/ROUT, HP-Amp, SPK-Amp ATT Select) is added [AK4537] AK4537 Yes (Stereo) Stereo Stereo Yes Yes Yes Yes AK4537 MICOUTL MICOUTR EXT/MICR INT/MICL ROUT LOUT RIN2 LIN2 LIN1 RIN1 2005/04 ...
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... Audio Serial Data Clock Pin 25 MCKO O Master Clock Output Pin No Connect This pin should be left floating. MS0202-E-04 PIN/FUNCTION Function 2 C Bus, “L”: 4-wire Serial - 5 - [AK4537] (PMMICR bit = “0”) (PMMICR bit = “1”) (PMMICL bit = “0”) (PMMICL bit = “1”) 2005/04 ...
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... LIN1 I Rch Analog Input 1 Pin (MIC Input) 52 RIN1 I Lch Analog Input 1 Pin (MIC Input) Note: All input pins except analog input pins (INT, EXT, LIN1, RIN1, MIN, BEEPM, BEEPL, BEEPR, LIN2 and RIN2) should not be left floating. MS0202-E-04 Function - 6 - [AK4537] 2005/04 ...
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... AKM assumes no responsibility for the usage beyond the conditions in this datasheet. MS0202-E-04 ABSOLUTE MAXIMUM RATINGS Symbol min AVDD DVDD PVDD HVDD (Note 2) GND1 (Note 2) GND2 (Note 2) GND3 IIN VINA VIND Ta Tstg Symbol min AVDD 2.4 DVDD 2.4 PVDD 2.4 HVDD 2 [AK4537] max Units 0.3 4.6 V 0.3 4.6 V 0.3 4.6 V 0 0.3 AVDD+0.3 V 0.3 DVDD+0 ...
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... DAC LOUT, ROUT L 1.94 1. IPGA ADC - 8 - [AK4537] typ max Units 2. 1. 0.5 0 +27 + Bits 0.228 Vpp 2.28 Vpp ...
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... HPL/HPR pin 6 Figure 2. Headphone-amp output circuit - 9 - [AK4537] typ max Units 0.31 - Vpp 3.96 4.36 Vpp 76 - dBFS 89 - dBFS ...
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... PMBPM=PMBPS= “1” and PMHPL=PMHPR= “0”. Note 21. All digital input pins are fixed to DVDD or DVSS. MS0202-E-04 min typ - - MOUT2 - 1. 1 [AK4537] max Units 1.98 Vpp 26 k 1.98 Vpp Vpp - 100 A 100 A 100 A 2005/04 ...
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... Note 24. These frequency responses scale with fs high-level and low frequency signal is input, the analog output clips to the full-scale. MS0202-E-04 FILTER CHARACTERISTICS 3.6V; fs=44.1kHz; DEM=OFF) Symbol min 27 24 16. [AK4537] typ max Units - 17.4 kHz 20.0 - kHz 21.1 - kHz - - kHz - dB 0 17 20.0 kHz 22.05 - kHz - - kHz - dB 0. ...
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... Duty 45 Duty - tBCK 312.5 tBCKL 130 tBCKH 130 tLRB 50 tBLR 50 S mode) tLRS - tBSD - tSDH 50 tSDS 50 fBCK - fBCK - dBCK - tMBLR 80 tBSD 80 tSDH 50 tSDS [AK4537] typ Max Units - - V - 30%DVDD 0 0 typ max Units - 12.288 MHz - 12.288 MHz - - ...
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... PMADL or PMADR “n” to SDTO valid (Note 31) Note 29. Data must be held long enough to bridge the 300ns-transition time of SCL. Note 30. The AK4537 can be reset by the PDN pin = “L”. Note 31. This is the count of LRCK “n” from the PMADL or PMADR bit = “1”. ...
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... LRCK BICK tBCKH MCKO dMCK 1000pF MCKI Input MS0202-E-04 1/fCLK tCLKL 1/fs tBCK tBCKL fMCK dMCK Figure 3. Clock Timing Measurement Point 100k AGND AGND Figure 4. MCKI AC Coupling Timing - 14 - [AK4537] VIH VIL VIH VIL VIH VIL 50%DVDD 1/fCLK tACW tACW VAC 2005/04 ...
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... Figure 5. Audio Interface Timing (Slave mode) LRCK tMBLR BICK SDTO SDTI Figure 6. Audio Interface Timing (Master mode) MS0202-E-04 tLRB tBSD tSDS tSDH dBCK tBSD tSDS tSDH - 15 - [AK4537] VIH VIL VIH VIL 50%DVDD VIH VIL VIH VIL 50%DVDD 50%DVDD VIH VIL 2005/04 ...
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... CCLK CDTI CDTO Figure 7. WRITE/READ Command Input Timing CSN CCLK CDTI D2 CDTO MS0202-E-04 tCSS tCCKL tCCKH tCDS tCDH C1 C0 Hi-Z tCSH D1 D0 Hi-Z Figure 8. WRITE Data Input Timing - 16 - [AK4537] VIH VIL VIH VIL VIH R/W VIL tCSW VIH VIL VIH VIL VIH VIL 2005/04 ...
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... D7 Figure 9. READ Data Output Timing 1 tCSW tCSH D1 D0 Figure 10. READ Data Output Timing [AK4537] VIH VIL VIH VIL VIH VIL D6 50%DVDD VIH ...
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... Start 2 Figure 11 Bus Mode Timing tPDV tPD Figure 12. Power Down & Reset Timing - 18 - [AK4537] VIH VIL tSP VIH VIL tSU:STO Stop VIH VIL ...
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... ASAHI KASEI „ Master Clock Source The AK4537 requires a master clock (MCLK). This master clock is input to the AK4537 by connecting a X’tal oscillator to XTI and XTO pins or by inputting an external CMOS-level clock to the XTI pin or by inputting an external clock that is greater than 50% of the DVDD level to the XTI pin through a capacitor. ...
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... AC Coupling Input C XTI External Clock XTO Figure 15. External Clock mode (Input : Note: This clock level must not exceed DVDD level 0.1 F) MS0202-E-04 MCKPD = "0" 25k PMXTL = "0" AK4537 MCKPD = "0" 25k PMXTL = "1" AK4537 50%DVDD [AK4537] 2005/04 ...
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... The phase between these clocks does not matter. LRCK and BICK must be present whenever the AK4537 is operating (PMADL bit = “1”, PMADR bit = “1” or PMDAC bit = “1”). If these clocks are not provided, the AK4537 may draw excess current due to its use of internal dynamically refreshed logic. If the external clocks are not present, place the AK4537 in power-down mode (PMADL bit = PMADR bit = PMDAC bit = “ ...
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... The phase between these clocks does not matter. LRCK and BICK should always be present whenever the AK4537 is in normal operation (PMADL bit = “1”, PMADR bit = “1” or PMDAC bit = “1”). If these clocks are not provided, the AK4537 may draw excess current due to its use of internal dynamically refreshed logic. If the external clocks are not present, place the AK4537 in power-down mode (PMADL bit = PMADR bit = PMDAC bit = “ ...
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... The M/S pin selects either master or slave modes. M/S pin = “H” selects master mode and “L” selects slave mode. The AK4537 outputs MCKO, BICK and LRCK in master mode. The AK4537 outputs only MCKO in slave mode, while BICK and LRCK must be input separately. ...
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... All data formats can be used in both master and slave modes. LRCK and BICK are output from AK4537 in master mode, but must be input to AK4537 in slave mode. If 16-bit data that ADC outputs is converted to 8-bit data by removing LSB 8-bit 16bit data is converted 8-bit data. And when the DAC playbacks this 8-bit data 8-bit data will be converted to 256 at 16-bit data and this is a large offset ...
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... Lch Data Figure 18. Mode 2 Timing - 25 - [AK4537 ...
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... ASAHI KASEI „ MIC Gain Amplifier AK4537 has a Gain Amplifier for Microphone input. This gain is 0dB or 20dB, selected by the MGAIN bit (Table 14). The typical input impedance is 30k . The mic gain amp of the AK4537 supports the following three cases: Internal MIC External ...
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... IPGA value is attenuated at the zero-detect points of the waveform. [2] ALC1 Recovery Operation The ALC1 recovery refers to the amount of time that the AK4537 will allow both Lch and Rch signal to exceed a predetermined limiting value prior to enabling the limiting function. The ALC1 recovery operation uses the WTM1-0 bits to define the wait period used after completing an ALC1 limiter operation. If Lch or Rch input signals are lower than the “ ...
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... Limiter = Zero crossing Enable Recovery Cycle = 16ms @ fs= 8kHz Limiter and Recovery Step = 1 Maximum Gain = +27.5dB Limiter Detection Level = -4dBFS ALC2 bit = “1” (default) * The value of IPGA should be the same or smaller than REF’ [AK4537] fs=16kHz fs=44.1kHz Data Operatio Data Operatio n n ...
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... ASAHI KASEI „ De-emphasis Filter The AK4537 includes the digital de-emphasis filter (tc = 50/ IIR filter. Setting the DEM1-0 bits enables the de-emphasis filter (Table 16). DEM1 „ Bass Boost Function The BST1-0 bits control the amount of low frequency boost applied to the DAC output signal (Table 17 the BST1-0 bits are set to “ ...
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... ASAHI KASEI „ Digital Attenuator The AK4537 has a channel-independent digital attenuator (256 levels, 0.5dB step, Mute). The attenuation level of each channel can be set by the ATTL/R7-0 bits. When the DATTC bit = “1”, the ATTL7-0 bits control both Lch and Rch attenuation levels. When the DATTC bit = “0”, the ATTL7-0 bits control Lch level and ATTR7-0 bits control Rch level. ...
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... BEEPM MS0202-E- 20k BPMHP Rf = 20k Rf = 20k 1/2 1/2 AK4537 Figure 25. Block Diagram of BEEP pins - 31 - [AK4537] 30% . BPSHP HPL MIX -20dB HPR MIX BPSHP BPSSP SPK MIX BPMSP 2005/04 ...
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... This fall time depends on the capacitor value connected with the MUTET pin. The time constant is = 100k x C when the capacitor value on MUTET pin is “C”. (4) Headphone-amp power-down (HPL, HPR bit= “1”). The outputs are HVSS. If the power supply is switched off or Headphone-amp is powered-down before the common voltage goes to HVSS, some POP noise occurs. MS0202-E-04 (3) ( [AK4537] 2005/04 ...
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... BOOST=MID 2.7V 152.5 63 10.0 105.8 43 4.8 71.2 27 10.0 49.7 20 4.8 Table 19. External Circuit Example - 33 - [AK4537 Output Power [mW] 3.0V 3.3V 12.4 15.0 6.0 7.2 12.4 15.0 6.0 7.2 2005/04 ...
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... When the SPPS bit is “0”, the Speaker-amp enters power-save-mode. In this mode, the SPP pin is placed in a Hi-Z state and the SPN pin goes to HVDD/2 voltage. And then the Speaker output gradually changes to the HVDD/2 voltage and this mode can reduce pop noise at power-up. When the AK4537 is powered down, pop noise can be also reduced by first entering power-save-mode. ...
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... MOUT2 pin is forced to VCOM voltage. The load impedance is 10k (min.). When the PMSPK bit is “0”, the Speaker-amp enters power-down-mode and the output is placed in a Hi-Z state. MS0202-E-04 20k 30% BPSSP 45%AVDD 20k 30% BPSSP 45%AVDD BEEPL BEEPR - 35 - [AK4537] SPK-Amp SPP SPN 2005/04 ...
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... Amp for mono line output has 6dB gain and -17dB gain that are set by the MOGN bit. MS0202-E-04 ATT IPGA Lch “MICL” “DAHS” Figure 31. Stereo Line Output ATT IPGA Lch “MICM” “DAMO” “MOGN” 1/2 1/2 -17dB/+6dB Figure 32. Mono Line Output - 36 - [AK4537] LOUT pin ROUT pin MOUT+ MOUT- 2005/04 ...
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... FS-2.1dB = -5.2dBV +6.0dB -3.3dBV -1.9dB +6.0dB +4.1dB -11.3dBV +8.1dB -15.3dBV FS-4.1dB = -7.2dBV +16.1dB -23.3dBV ALC2 SPK-AMP - 37 - [AK4537] ALC2 Recovery operation 7.2dBV 2048/fs = 46.4ms@fs=44.1kHz 512/fs = 46.4ms@fs=11.025kHz O (Timeout = 2048/fs) 1dB step 0.8dBV(150mW@8ohm) 0dBV -1.2dBV Full-differential Single-ended -5.2dBV -7.2dBV -10dBV -20dBV ...
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... Figure 34. Speaker-amp Output Level Diagram (HVDD=3.3V, DATT= 8.0dB, SPKG bit= “1”, ALC2= “1”) MS0202-E-04 FS-2.1dB = -5.2dBV +8.2dB -3.3dBV +8.2dB -1.9dB +2.2dB +2.2dB +4.1dB -11.3dBV +8.1dB -15.3dBV FS-4.1dB = -7.2dBV +16.1dB -23.3dBV ALC2 SPK-AMP - 38 - [AK4537] 3.0dBV(250mW@8ohm) 1.0dBV 0dBV Full-differential -3.0dBV Single-ended -5.0dBV -10dBV -20dBV -30dBV 2005/04 ...
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... Hi Figure 35. Serial Control I/F Timing - 39 - [AK4537 ...
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... These two bits identify the specific device on the bus. The hard-wired input pins (CAD1 and CAD0 pins) set these device address bits (Figure 37). If the slave address matches that of the AK4537, the AK4537 generates an acknowledge and the operation is executed. The master must generate the acknowledge-related clock pulse and release the SDA line (HIGH) during the acknowledge clock pulse (Figure 43). A R/W bit value of “ ...
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... ASAHI KASEI (2)-2. READ Operations Set the R/W bit = “1” for the READ operation of the AK4537. After transmission of data, the master can read the next address’s data by generating an acknowledge instead of terminating the write cycle after the receipt of the first data word. ...
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... MASTER S START CONDITION SDA SCL MS0202-E-04 Figure 42. START and STOP Conditions Figure 43. Acknowledge on the I C-Bus data line change stable; of data data valid allowed 2 Figure 44. Bit Transfer on the I C-Bus - 42 - [AK4537] P stop condition not acknowledge acknowledge 8 9 clock pulse for acknowledgement 2005/04 ...
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... REF5 REF4 0 IPGAL6 IPGAL5 IPGAL4 ATTL6 ATTL5 ATTL4 ATTR6 ATTR5 ATTR4 ATTS2 ATTS1 ATTS0 0 IPGAR6 IPGAR5 IPGAR4 INR - 43 - [AK4537 PMMO PMADL PMIPGL PMMICL PMSPK PMHPL PMHPR PMDAC BPSSP BPMSP ALCS MOUT2 BPSHP BPMHP HPL HPR MCKO BF DIF1 DIF0 ...
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... Power down Power up 0 Power up Power down 1 Power up Power up Table 22. ADC Block Power Control PMIPGL MIC-Amp 0 Power down Power down 1 Power down 0 Power up 1 Power [AK4537 PMMO PMADL PMIPGL PMMICL R/W R/W R/W R Digital L/R Power down Power up Power up Power up ...
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... PLL Mode and Power up PMXTL: X’tal Oscillation Block Power Control 0: Power down (Default) 1: Power up MCKPD: XTI pin pull down control 0: Master Clock input enable 1: Pull down by 25k (Default) MS0202-E- PMXTL PMPLL SPKG PMSPK R/W R/W R/W R [AK4537 PMHPL PMHPR PMDAC R/W R/W R 2005/04 ...
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... When the PSMO bit = “0”, Mono Line Output is in power save mode and the MOUT+ and MOUT- pins output 0.45 x AVDD voltage. MOGN: Gain control for mono output 0: +6dB (Default) 1: -17dB MS0202-E- PSMO DAMO MICM R/W R/W R/W R [AK4537 BPSSP BPMSP ALCS MOUT2 R/W R/W R/W R 2005/04 ...
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... ASAHI KASEI DAHS DAC BPMSP BEEPM BPSSP BEEPL BEEPR MS0202-E-04 MOUT2 MIX ALC2 Figure 45. Speaker-amp switch control - 47 - [AK4537] ALCS SPK 2005/04 ...
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... DAC signal is mixed to Stereo Line Output, Headphone-amp and MOUT2 at the DAHS bit = “1”. DAHS DAC BPMHP BEEPM BPSHP BEEPL BEEPR MS0202-E- PSLO 0 MICL R/W R HPL HPR Figure 46. Headphone-amp switch control - 48 - [AK4537 BPSHP BPMHP HPL HPR R/W R/W R/W R HPL MUTE HPR MUTE 2005/04 ...
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... PS1-0: Output Master Clock Select (see Table 4, Table 8) Default: “00” (256fs) PLL1-0: Input Master Clock Select at PLL Mode (see Table 2) Default: “00” (12.288MHz) MS0202-E- PLL1 PLL0 PS1 PS0 R/W R/W R/W R [AK4537 MCKO BF DIF1 DIF0 R/W R/W R/W R 2005/04 ...
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... When the HPM bit = “1”, (L+R)/2 signals are output to Lch and Rch of the Headphone-amp. Both PMHPL and PMHPR bits should be “1” when HPM bit is “1”. FS2-0: Sampling frequency modes (see Table 3, Table 7) Default: “000” (fs=44.1kHz) MS0202-E- FS2 FS1 FS0 0 R/W R/W R [AK4537 HPM LOOP SPPS RD R/W R/W R 2005/04 ...
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... Soft Mute Time Select (see Table 24) Default: “00” (1024/fs) TM1 MS0202-E- TM1 TM0 SMUTE DATTC R/W R/W R/W R TM0 Cycle 0 0 1024/fs Default 0 1 512/ 256/ 128/fs Table 24. Soft Mute Time Setting - 51 - [AK4537 BST1 BST0 DEM1 DEM0 R/W R/W R/W R 2005/04 ...
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... When IPGAC= “1”, IPGAL6-0 bits control both Lch and Rch at same time. IPGAR6-0 bits are not changed when the IPGAL6-0 bits are written. MS0202-E- IPGAC MPWRE RD R/W R [AK4537 MPWRI MICAD MSEL MGAIN R/W R/W R/W R 2005/04 ...
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... Zero Crossing Timeout Period 8kHz 16kHz 128/fs 16ms 8ms 256/fs 32ms 16ms 512/fs 64ms 32ms 1024/fs 128ms 64ms Table 27. Zero Crossing Timeout Period - 53 - [AK4537 WTM1 WTM0 LTM1 LTM0 R/W R/W R/W R 44.1kHz Default ...
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... ALC1 Recovery Waiting Counter Reset Level 6.0dBFS ADC Input 4.0dBFS ADC Input RATT GAIN STEP 0 1 Default 1 2 LMAT0 ATT STEP 0 1 Default Table 30. ALC1 Limiter ATT Step Setting - 54 - [AK4537 LMAT1 LMAT0 RATT LMTH R/W R/W R/W R 8.0dBFS Default 6.0dBFS 2005/04 ...
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... DATA (HEX Table 31. Setting Reference Value at ALC1 Recovery Operation MS0202-E- REF6 REF5 REF4 RD R/W R/W R GAIN (dB) MIC Input LINE Input +27.5 +12.0 +27.0 +11.5 +26.5 +11 +19.0 +3 +15.5 +0 +0.0 -15 5.0 20.5 5.5 21.0 6.0 21.5 6.5 22.0 7.0 22.5 7.5 23.0 8.0 23 [AK4537 REF3 REF2 REF1 REF0 R/W R/W R/W R STEP Default 0.5dB 2005/04 ...
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... Table 32. Input Gain Setting ATTL6 ATTL5 ATTL4 ATTR6 ATTR5 ATTR4 R/W R/W R/W R [AK4537 IPGAL3 IPGAL2 IPGAL1 IPGAL0 IPGAR3 IPGAR2 IPGAR1 IPGAR0 R/W R/W R/W R STEP Default 0.5dB ATTL3 ATTL2 ATTL1 ATTL0 ATTR3 ATTR2 ATTR1 ATTR0 ...
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... ATTM: Attenuator control for signal from IPGA Lch to Mono Mixer 0: OFF. 0dB (Default) 1: ON. –4dB MS0202-E- ATTS2 ATTS1 ATTS0 R/W R/W R Attenuation 7H -6dB 6H 9dB 5H Default 12dB 4H 15dB 3H 18dB 2H 21dB 1H 24dB 0H -27dB Table 33. Attenuator Table - 57 - [AK4537 2005/04 ...
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... Power down Power up 0 Power up Power down 1 Power up Power up Table 34. ADC Block Power Control PMIPGR MIC-Amp 0 Power down Power down 1 Power down 0 Power up 1 Power [AK4537 INL PMADR PMIPGR PMMICR R/W R/W R/W R Digital L/R Power down Power up Power up Power up ...
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... PVSS 12 VCOC 10k 4. Reset Notes: - AVSS, DVSS, PVSS and HVSS of the AK4537 should be distributed separately from the ground of external controllers. - Values of R and C in Figure 47 should depend on system. - All input pins should not be left floating. MS0202-E-04 SYSTEM DESIGN ...
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... The Mic, Line and Beep inputs are single-ended. The input signal range scales with nominally at 0.06 x AVDD Vpp for the Mic input and 0.6 x AVDD Vpp for the Beep input, centered around the internal common voltage (0.45 x AVDD). Usually the input signal is AC coupled using a capacitor. The cut-off frequency (1/2 RC). The AK4537 can accept input voltages from AVSS to AVDD. ...
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... Power Supply (2) PDN pin = “L” “H” “L” time of 150ns or more is needed to reset the AK4537. (3) Power up VCOM : PMVCM bit = “0” VCOM should first be powered up before the other block operates. (4) Set up register 02H : MOUT2 bit = ALCS bit = “0” ...
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... XX Figure 49. Clock Set Up Sequence(1) “0” and power-up the X’tal oscillator: PMXTL bit “1” “1” [AK4537 rts ...
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... Figure 50. Clock Set Up Sequence(2) “0” and and power-up the X’tal oscillator: PMXTL “1” “1” and set up MCKO output frequency (PS1-0 bits [AK4537 ...
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... XX Figure 51. Clock Set Up Sequence(3) “0” “1” “1”. “1” [AK4537 r exte r r starts ...
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... Input M aster Frequency : 256fs O utput M aster Frequency : 64fs XX Input Input Output Figure 53. Clock Set Up Sequence(5) “0” [AK4537 r: ata: extern r: ata r: ata r ata:00 H ...
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... MIC block is powered-down. If the registers for the ALC1 operation are also changed when the sampling frequency is changed, it should be done after the AK4537 goes to the manual mode (ALC1 bit = “0”) or MIC block is powered-down (PMMICL bit = “0”). IPGA gain is reset when PMMICL =PMMICR=PMIPGL=PMIPGR= “ ...
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... X ’ lin “1 ” lt tte ...
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... Hi-Z Figure 56. Speaker-Amp Output Sequence “1” “0” [AK4537 ’ “ 1 ” ...
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... Figure 58. Stop of Clock Sequence(2) “0” “0”, MCKPD = “0” [AK4537 r r “1” ...
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... When the external MCLK becomes Hi-Z or the external MCLK is input by AC couple, MCKI pin should be pulled down. (2) Stop an external MCLK „ Power down Power down VCOM(PMVCM= “1” AK4537 is also powered-down by PDN pin = “L”. When PDN pin = “L”, the registers are initialized. MS0202-E- Figure 59. Stop of Clock Sequence(3) “1” ...
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... Note) The part of black at four corners on reverse side must not be soldered and must be open. „ Material & Lead finish Package molding compound: Lead frame material: Lead frame surface treatment: MS0202-E-04 PACKAGE 0.60 + 0. C0.6 45° Epoxy Cu Solder (Pb free) plate - 71 - [AK4537] 0.20 + 0. 45° 0.40 0.18 ± 0.05 0.05 M 2005/04 ...
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... ASAHI KASEI XXXXXXX : MS0202-E-04 MARKING AKM AK4537VN XXXXXXX 1 Date code identifier (7 digits [AK4537] 2005/04 ...
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... DAC data should be soft-muted or “0”. In case of the ADC(PMADL bit = “1” or PMADR bit = “1”), the ADC data acquired during the frequency change may be erroneous and therefore should not be used.” is deleted [AK4537] 0.22 F 20% capacitor and “This pin 2005/04 ...
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... Register Definitions (Addr=00H) “IPGA gain is reset when PMMICL=PMMICR=PMIPGL=PMIPGR= “0”.” is added. “The paths from BEEP to HP-Amp and SPK-Amp can operate without these clocks.” is added [AK4537] the IPGAL6-0 and timeout (the write 2 C bus is available 2005/04 ...
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... S regardless of DIF1-0 bits setting.] is added. 32 Headphone Output Rise/fall time constant: = 250ms(max). Time until the common goes to HVSS when PMHPL/R bits = “1” Æ “0”: 500ms(max). 66 Headphone Output Sequence (6), (9) Rise/fall time constant: = 250ms(max [AK4537] operation. When when PMMICL 10H(0dB) 10H 2005/04 ...
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... AKM harmless from any and all claims arising from the use of said product in the absence of such notification. MS0202-E-04 Page Contents 1 Features SPK-AMP Output Power: 300mW Æ 400mW 34-35 SPK-AMP “Connection Example for 400mW output” is added. IMPORTANT NOTICE - 76 - [AK4537] 2005/04 ...