ak4537 AKM Semiconductor, Inc., ak4537 Datasheet - Page 45

• Manufacturer Part Number: ak4537
• Description: 16-bit 6 Stereo Codec With Mic/hp/spk-amp
• Manufacturer: AKM Semiconductor, Inc.

ASAHI KASEI
MS0202-E-04
Addr
01H
PMVCM: VCOM Block Power Control
PMDAC: DAC Block Power Control
PMHPR: Rch of Headphone-Amp Common Voltage Power Control
PMHPL: Lch of Headphone-Amp Common Voltage Power Control
PMSPK: Speaker Block Power Control
SPKG: Select Speaker-Amp Output Power (8 load)
PMPLL: PLL Block Power Control Select
PMXTL: X’tal Oscillation Block Power Control
MCKPD: XTI pin pull down control
0: Power down (Default)
1: Power up
Each block can be powered down respectively by writing “0” in each bit. When the PDN pin is “L”, all blocks are
powered down.
When all bits except MCKPD bit are “0” in the 00H, 01H and 10H addresses, all blocks are powered down. The
register values remain unchanged. IPGA gain is reset when PMMICL=PMMICR=PMIPGL=PMIPGR= “0” (refer
to the IPGAL6-0 and IPGAR6-0 bits description).
When any of the blocks are powered up, the PMVCM bit must be set to “1”.
MCLK, BICK and LRCK must always be present unless PMMICL=PMMICR=PMIPGL=PMIPGR=PMADCL
=PMADR=PMDAC=PMSPK= “0” or PDN pin = “L”. The paths from BEEP to HP-Amp and SPK-Amp can
operate without these clocks.
0: Power down (Default)
1: Power up
0: Power down (Default)
1: Power up
0: Power down (Default)
1: Power up
0: Power down (Default)
1: Power up
0: 150mW (Default)
1: 300mW(ALC2 = “0”) or 250mW(ALC2 = “1”)
0: EXT Mode and Power down (Default)
1: PLL Mode and Power up
0: Power down (Default)
1: Power up
0: Master Clock input enable
1: Pull down by 25k (Default)
Register Name
Power Management 2
Default
R/W
MCKPD
R/W
D7
1
PMXTL
R/W
D6
0
- 45 -
PMPLL
R/W
D5
0
SPKG
R/W
D4
0
PMSPK
R/W
D3
0
PMHPL
R/W
D2
0
PMHPR
R/W
D1
0
[AK4537]
2005/04
PMDAC
R/W
D0
0