zl50118gag2 Zarlink Semiconductor, zl50118gag2 Datasheet - Page 30
zl50118gag2
Manufacturer Part Number
zl50118gag2
Description
32 Channel 1 T1/e1 Cesop Processor With Single Ethernet Interface
Manufacturer
Zarlink Semiconductor
Datasheet
1.ZL50118GAG2.pdf
(94 pages)
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4.2
All PAC Interface signals are 5 V tolerant.
All PAC Interface outputs are high impedance while System Reset is LOW.
TDM_CLKiP
TDM_CLKiS
PLL_PRI
PLL_SEC
PAC Interface
Signal
I/O
OT
OT
I D
I D
V4
U4
Y9
W10
Table 5 - PAC Interface Package Ball Definition
ZL50115/16/17/18/19/20
Package Balls
Zarlink Semiconductor Inc.
30
Primary reference clock input. Should be
driven by external clock source to provide
locking reference to internal / optional
external DPLL in TDM master mode. Also
provides PRS clock for RTP timestamps in
synchronous modes.
Acceptable frequency range: 8 kHz -
34.368 MHz (generally should be between
10 MHz and 25 MHz as per ITU-T Y.1413).
Secondary reference clock input. Backup
external reference for automatic switch-over
in case of failure of TDM_CLKiP source.
Primary reference output to optional
external DPLL.
Multiplexed & frequency divided reference
output for support of optional external DPLL.
Expected frequency range:
8 kHz - 16.384 MHz.
Secondary reference output to optional
external DPLL Multiplexed & frequency
divided reference output for support of
optional external DPLL.
Expected frequency range:
8 kHz - 16.384 MHz.
Description
Data Sheet
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