zl50118gag2 Zarlink Semiconductor, zl50118gag2 Datasheet - Page 81

• Manufacturer Part Number: zl50118gag2
• Description: 32 Channel 1 T1/e1 Cesop Processor With Single Ethernet Interface
• Manufacturer: Zarlink Semiconductor

12.6.5
Note1:
(ZLAN-239) for workaround when using the TBI interface.
GTXCLK period
GTXCLK high wide time
GTXCLK low wide time
TXD[9:0] Output Delay
(GTXCLK rising edge)
RCB0/RBC1 period
RCB0/RBC1 high wide time
RCB0/RBC1 low wide time
RCB0/RBC1 rise time
RCB0/RBC1 fall time
RXD[9:0] setup time (RCB0
rising edge)
RXD[9:0] hold time (RCB0
rising edge)
REFCLK period
REFCLK high wide time
REFCLK low wide time
These measurements were obtained through simulation and lab measurement using a 10pF load. See application note
Signal_Detect
TBI Interface Timing
Parameter
GTXCLK
TXD[9:0]
/I/
/S/ /D/ /D/ /D/ /D/ /D/ /D/ /D/ /D/ /D/ /D/ /D/ /D/ /D/ /D/ /D/ /T/ /R/ /I/
t
GC
Symbol
Figure 36 - TBI Transmit Timing Diagram
t
t
t
t
t
t
t
t
t
t
t
t
t
t
GC
GH
RC
RH
RR
DH
GL
DV
RL
RF
DS
FC
FH
Table 34 - TBI Timing - 1000 Mbps
FL
ZL50115/16/17/18/19/20
Zarlink Semiconductor Inc.
t
DV
Min.
7.5
2.5
2.5
0.1
7.5
2.5
2.5
15
5
5
2
1
-
-
81
1000 Mbps
Typ.
16
-
-
-
-
-
-
-
-
-
-
-
-
-
Max.
8.5
2.4
8.5
17
2
2
-
-
-
-
-
-
-
-
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Load = 10 pF
Data Sheet
Note 1
Notes