zl50118gag2 Zarlink Semiconductor, zl50118gag2 Datasheet - Page 50

• Manufacturer Part Number: zl50118gag2
• Description: 32 Channel 1 T1/e1 Cesop Processor With Single Ethernet Interface
• Manufacturer: Zarlink Semiconductor

Each of the 11 data flows uses the Task Manager to route packet information to the next block or interface for
onward transmission. The flow is determined by the Type field in the Task Message (see ZL50115/16/17/18/19/20
Programmers Model).
6.3
The quality of the 100 MHz SYSTEM_CLK or the oscillator that drives SYSTEM_CLK directly impacts the adaptive
clock recovery performance. Zarlink has a recommended oscillator and guidelines for the selection of an oscillator.
Please review application note ZLAN-153 “External Component Selection” before choosing an oscillator.
6.4
The ZL5011x family offers the following types of TDM service across the packet network:
Unstructured services are fully asynchronous, and include full support for clock recovery on a per stream basis.
Both adaptive and differential clock recovery mechanisms can be used.
Structured services are synchronous, with all streams driven by a common clock and frame reference. These
services can be offered in two ways:
•
•
In either structured mode, N x 64 Kbps trunking is supported as detailed in “Payload Order” on page 54.
The ZL5011x supports structured mode or unstructured mode, however it does not support structured mode and
unstructured mode at the same time, all ports are either structured or unstructured. In structured mode, all TDM
inputs must be synchronous.
Unstructured
asynchronous
Structured synchronous
(N x 64 Kbps)
may be locked to an incoming clock or frame reference
all streams
Synchronous master mode - the ZL5011x provides a common clock and frame pulse to all streams, which
Synchronous slave mode - the ZL5011x accepts a common external clock and frame pulse to be used by
SYSTEM_CLK Considerations
TDM Interface
Service type
Table 20 - TDM Services Offered by the ZL50115/16/17/18/19/20 Family
1. This flow is for loopback and may be helpful for test purposes
Flow Number
T1, E1, J2, E3 and T3
T1, E1 and J2
Framed TDM data
streams at 2.048 and
8.192 Mbps
Table 19 - Standard Device Flows (continued)
10
11
TDM interface
1
1
ZL50115/16/17/18/19/20
Zarlink Semiconductor Inc.
50
Bit clock in and out
Data in and out
Bit clock out
Frame pulse out
Data in and out
Bit clock in
Frame in
Data in and out
Flow Through Device
Interface type
TDM to (TM) to TDM
PKT to (TM) to PKT
Line interface unit
Framers
TDM backplane (master)
Framers
TDM backplane (slave)
Interfaces to
Data Sheet