zl50118gag2 Zarlink Semiconductor, zl50118gag2 Datasheet - Page 60

• Manufacturer Part Number: zl50118gag2
• Description: 32 Channel 1 T1/e1 Cesop Processor With Single Ethernet Interface
• Manufacturer: Zarlink Semiconductor

8.4
During normal operation, a situation may arise where a Loss of Service occurs. This may be caused by a disruption
in the transmission line due to engineering works or cable disconnection, for example. The locally detected LOS
should be transferred across the emulated T1/E1 to the far end. The far end, in turn, should propagate AIS
downstream.
The handling of LOS over a CESoP connection is typically performed using (setting/clearing) the L bit in the
CESoPSN or SAToP control word of the packet header.
Refer to Application Note ZLAN-159, section 4.1 for details on a variety of different ways that LOS may be handled
in an application.
8.5
To power up the ZL5011x the following procedure must be used:
•
•
•
•
•
This is illustrated in the diagram shown in Figure 22.
8.6
The JTAG interface is used to access the boundary scan logic for board level production testing.
The I/O supply should lead the Core supply, or both can be brought up together
The I/O supply must never exceed the Core supply by more than 2.0VDC
The Core supply must never exceed the I/O supply by more than 0.5V
Both the Core supply and the I/O supply must be brought up together
The System Reset and, if used, the JTAG Reset must remain low until at least 100 µs after the 100 MHz
system clock has stabilised. Note that if JTAG Reset is not used it must be tied low
Loss of Service (LOS)
Power Up Sequence
JTAG Interface and Board Level Test Features
SCLK
V
RST
DD
<0.5 V
DC
Figure 22 - Powering Up the ZL5011x
ZL50115/16/17/18/19/20
Zarlink Semiconductor Inc.
10 ns
60
> 100 µs
DC
Core supply (1.8 V)
I/O supply (3.3 V)
Data Sheet
t
t
t