zl50118gag2 Zarlink Semiconductor, zl50118gag2 Datasheet - Page 51

• Manufacturer Part Number: zl50118gag2
• Description: 32 Channel 1 T1/e1 Cesop Processor With Single Ethernet Interface
• Manufacturer: Zarlink Semiconductor

6.4.1
The TDM Interface contains two basic types of interface: unstructured clock and data, for interfacing directly to a
line interface unit; or structured, framed data, for interfacing to a framer or TDM backplane.
Unstructured data is treated asynchronously, with every stream using its own clock. Clock recovery is provided on
each output stream, to reproduce the TDM service frequency at the egress of the packet network. Structured data is
treated synchronously, i.e., all data streams are timed by the same clock and frame references. These can either be
supplied from an external source (slave mode) or generated internally using the on-chip stratum 4/4E PLL (master
mode).
6.4.2
The ZL5011x is programmable such that the frame/clock polarity and clock alignment can be set to any desired
combination. Table 21 shows a brief summary of four different TDM formats; ST-BUS, H.110, H-MVIP, and Generic
(synchronous mode only), for more information see the relevant specifications shown. There are many additional
formats for TDM transmission not depicted in Table 21, but the flexibility of the port will cover almost any scenario.
The overall data format is set for the entire TDM Interface device, rather than on a per stream basis. It is possible to
control the polarity of the master clock and frame pulse outputs, independent of the chosen data format (used when
operating in synchronous master mode).
H-MVIP
Generic
Format
ST-bus
H.110
Data
Table 21 - Some of the TDM Port Formats Accepted by the ZL50115/16/17/18/19/20 Family
TDM Interface Block
Structured TDM Port Data Formats
(Mbps)
2.048
2.048
8.192
8.192
2.048
2.048
8.192
2.048
8.192
Data
Rate
channels
Number
frame
128
128
128
128
per
32
32
32
32
32
of
ZL50115/16/17/18/19/20
16.384
16.384
Clock
(MHz)
2.048
4.096
8.192
2.048
4.096
8.192
Freq.
2.048
Zarlink Semiconductor Inc.
Nominal
Frame
Width
Pulse
(ns)
244
244
122
244
244
244
488
122
61
51
Negative
Negative
Negative
Negative
Negative
Negative
Negative
Polarity
Positive
Positive
Frame
Pulse
Falling
Falling
Falling
Falling
Rising
Rising
Rising
Rising
Rising
clock
Frame Boundary
Edge
Edge
Edge
Edge
Edge
Edge
Edge
Edge
edge
Alignment
Straddles
boundary
Straddles
boundary
Straddles
boundary
Straddles
boundary
Straddles
boundary
Straddles
boundary
Straddles
boundary
edge of
edge of
frame
Rising
Rising
pulse
clock
clock
Data Sheet
MSAN-126
Standard
(Issue 4)
Release
H-MVIP
Zarlink
Rev B
ECTF
H.110
1.1a