am79c30a Advanced Micro Devices, am79c30a Datasheet - Page 85
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am79c30a
Manufacturer Part Number
am79c30a
Description
Digital Subscriber Controller ?dsc ?circuit
Manufacturer
Advanced Micro Devices
Datasheet
1.AM79C30A.pdf
(101 pages)
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Notes:
1. For PPCR2(0) = 0, SBIN data is sampled on the rising edge of SCLK; SBOUT data is changed on the falling edge of SCLK.
2. T1 width is eight SCLK periods.
Notes:
1. CH2STRB timing is identical to SFS timing but delayed by eight SCLK cycles.
2. This timing diagram reflects SCLK for PPCR2(0) = 0. For PPCR2(0) = 1, the diagram is identical except that the SCLK
SBIN or SBOUT
For PPCR2(0) = 1, SBIN data is sampled on the falling edge of SCLK; SBOUT data is changed on the rising edge of SCLK.
waveform should be inverted.
BCL/CH2STRB
MCLK (6.144 MHz)
SCLK
SFS
SCLK (192 kHz)
*SFS (8 kHz)
SBOUT
SBIN
Ta
Figure 36. SBP Mode MCLK/SCLK/SFS Timing
T1
Bd
Tb
t
MCSC
Figure 35. SBP Mode Timing
Am79C30A/32A Data Sheet
t
t
CHFS
CLDO
Tp
t
DICH
T1
Be
t
CHDZ
t
CLDO
Bf
t
CHFS
09893H-28
09893H-27
85