s71gl128nb0 Meet Spansion Inc., s71gl128nb0 Datasheet - Page 134

• Manufacturer Part Number: s71gl128nb0
• Description: Stacked Multi-chip Product Mcp 512/256/128 Megabit 32/16/8 M X 16-bit Cmos 3.0 Volt-only Mirrorbittm Page-mode Flash Memory With 32 Megabit 2m X 16-bit Psram
• Manufacturer: Meet Spansion Inc.

AC Characteristics
Notes:
1. Maximum value is applicable if CE1# is kept at Low without any address change. If the relaxation is needed by system
2. Minimum value must be equal or greater than the sum of write pulse (t
3. Write pulse is defined from High to Low transition of CE1#, WE#, or LB#/UB#, whichever occurs last.
4. Applicable for byte mask only. Byte mask setup time is defined to the High to Low transition of CE1# or WE# whichever
5. Applicable for byte mask only. Byte mask hold time is defined from the Low to High transition of CE1# or WE# whichever
6. Write recovery is defined from Low to High transition of CE1#, WE#, or LB#/UB#, whichever occurs first.
7. t
8. If OE# is Low after minimum t
9. If OE# is Low after new address input, read cycle is initiated. In other word, OE# must be brought to High at the same time
134
Write Cycle Time
Address Setup Time
CE1# Write Pulse Width
WE# Write Pulse Width
LB#/UB# Write Pulse Width
LB#/UB# Byte Mask Setup
Time
LB#/UB# Byte Mask Hold
Time
Write Recovery Time
CE1# High Pulse Width
WE# High Pulse Width
LB#/UB# High Pulse Width
Data Setup Time
Data Hold Time
OE# High to CE1# Low Setup
Time for Write
OE# High to Address Setup
Time for Write
LB# and UB# Write Pulse
Overlap
operation, please contact local Spansion representative for the relaxation of 1µs limitation.
occurs last.
occurs first.
CE1# is brought to Low. Once read cycle is initiated, new write pulse should be input after minimum t
or before new address valid. Once read cycle is initiated, new write pulse should be input after minimum t
bus is in High-Z.
WPH
minimum is absolute minimum value for device to detect High level. And it is defined at minimum V
Write Operation
Parameter
OHCL
Symbol
t
t
t
t
t
OHCL
t
t
t
t
t
t
t
t
t
t
BWO
t
WHP
BHP
OES
WC
CW
WP
BW
WR
BH
DS
DH
AS
BS
CP
, read cycle is initiated. In other words, OE# must be brought to High within 5ns after
Min.
7.5
70
45
45
45
10
10
15
30
-5
-5
-5
0
0
0
0
A d v a n c e
16M
1000
1000
1000
Max.
pSRAM Type 7
—
—
—
—
—
—
—
—
—
—
—
—
—
Min.
7.5
65
40
40
40
–5
–5
12
12
12
–5
30
0
0
0
0
I n f o r m a t i o n
32M
CW
1000
1000
1000
Max.
—
—
—
—
—
—
—
—
—
—
—
—
—
, t
WP
or t
Min.
7.5
65
40
40
40
–5
–5
12
12
12
–5
30
BW
0
0
0
0
) and write recovery time (t
64M
1000
1000
1000
Max.
—
—
—
—
—
—
—
—
—
—
—
—
—
pSRAM_Type07_13_A0 May 4, 2004
Unit
RC
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
is met.
IH
RC
level.
is met and data
Notes
WR
1,2
3
3
3
3
4
5
6
7
8
9
).