s71pl129ja0 Meet Spansion Inc., s71pl129ja0 Datasheet - Page 132

• Manufacturer Part Number: s71pl129ja0
• Description: Stacked Multi-chip Product Mcp Flash Memory And Psram 128 Megabit 8m X 16-bit Cmos 3.0 Volt-only Simultaneous Operation, Page Mode Flash Memory With 64/32/16 Megabit 4m/2m/1m X 16-bit Pseudo-static Ram
• Manufacturer: Meet Spansion Inc.

132
Sleep (default)
4M Partial
8M Partial
Power Down Program Sequence
Address Key
32M
N/A
The program requires 6 read/write operations with a unique address. Between
each read/write operation requires that device be in standby mode. The following
table shows the detail sequence.
The first cycle reads from the most significant address (MSB).
The second and third cycle are to write back the data (RDa) read by first cycle.
If the second or third cycle is written into the different address, the program is
cancelled, and the data written by the second or third cycle is valid as a normal
write operation.
The fourth and fifth cycles write to MSB. The data from the fourth and fifth cycles
is “don’t care.” If the fourth or fifth cycles are written into different address, the
program is also cancelled but write data might not be written as normal write
operation.
The last cycle is to read from specific address key for mode selection.
Once this program sequence is performed from a P artial mode to the other Partial
mode, the written data stored in memory cell array can be lost. So, it should per-
form this program prior to regular read/write operation if Partial mode is used.
The address key has following format.
Mode
Sleep (default)
16M Partial
8M Partial
Cycle #
2nd
3rd
4th
5th
6th
1st
64M
N/A
Operation
Write
Write
Write
Write
Read
Read
A d v a n c e
A21
1
1
1
1
pSRAM Type 7
3FFFFFh (MSB)
Address Key
3FFFFFh
3FFFFFh
3FFFFFh
3FFFFFh
Address
A20
I n f o r m a t i o n
1
1
0
0
Read Data (RDa)
Read Data (RDb)
Address
Don’t Care (X)
A19
1
0
1
0
Data
RDa
RDa
X
pSRAM_Type07_13_A1 November 2, 2004
A18 - A0
1
1
1
1
3FFFFFh
37FFFFh
2FFFFFh
27FFFFh
Binary