s71pl129ja0 Meet Spansion Inc., s71pl129ja0 Datasheet - Page 20

• Manufacturer Part Number: s71pl129ja0
• Description: Stacked Multi-chip Product Mcp Flash Memory And Psram 128 Megabit 8m X 16-bit Cmos 3.0 Volt-only Simultaneous Operation, Page Mode Flash Memory With 64/32/16 Megabit 4m/2m/1m X 16-bit Pseudo-static Ram
• Manufacturer: Meet Spansion Inc.

20
Simultaneous Read/Write Operation
Bank 1A
Bank 1B
Bank
Random Read (Non-Page Read)
Address access time (t
output data. The chip enable access time (t
dresses and stable CE# to valid data at the output inputs. The output enable
access time is the delay from the falling edge of the OE# to valid data at the out-
put inputs (assuming the addresses have been stable for at least t
Page Mode Read
The device is capable of fast page mode read and is compatible with the page
mode Mask ROM read operation. This mode provides faster read access speed for
random locations within a page. Address bits Amax–A3 select an 8 word page,
and address bits A2–A0 select a specific word within that page. This is an asyn-
chronous operation with the microprocessor supplying the specific word location.
The random or initial page access is t
cesses (as long as the locations specified by the microprocessor falls within that
page) is equivalent to t
reassertion of CE1# or CE#2 for subsequent access has access time of t
t
should be used to gate data to the output inputs if the device is selected. Fast
page mode accesses are obtained by keeping Amax–A3 constant and changing
A2–A0 to select the specific word within that page.
In addition to the conventional features (read, program, erase-suspend read, and
erase-suspend program), the device is capable of reading data from one bank of
memory while a program or erase operation is in progress in another bank of
memory (simultaneous operation). The bank can be selected by bank addresses
(A21–A19) with zero latency.
The simultaneous operation can execute multi-function mode in the same bank.
CE
. Here again, CE1# /CE#2 selects the device and OE# is the output control and
Word 0
Word 1
Word 2
Word 3
Word 4
Word 5
Word 6
Word 7
Word
ACC
PACC
CE1#
0
0
) is equal to the delay from stable addresses to valid
Table 2. Page Select
. When CE1# and CE#2 are deasserted (= V
A d v a n c e
S29PL129J for MCP
ACC
A2
0
0
0
0
1
1
1
1
or t
CE
I n f o r m a t i o n
CE
) is the delay from the stable ad-
and subsequent page read ac-
CE2#
1
1
A1
0
0
1
1
0
0
1
1
ACC
–t
OE
S29PL129J_MCP_00_A0 June 4, 2004
IH
ACC
time).
), the
PL129J: A21–A20
01, 10, 11
or
00
A0
0
1
0
1
0
1
0
1