scn68652ac2n40 NXP Semiconductors, scn68652ac2n40 Datasheet - Page 20

• Manufacturer Part Number: scn68652ac2n40
• Description: Scn2652/scn68652 Multi-protocol Communications Controller Mpcc
• Manufacturer: NXP Semiconductors

Philips Semiconductors
TIMING DIAGRAMS
TYPICAL APPLICATIONS
1995 May 1
Multi-protocol communications controller (MPCC)
NOTES:
1. At the end of a BOP message, RxSA goes high when FLAG detection (S/F 1) forces REOm to be set. Processor should read the last data character (RDSR
2. RxE must be dropped for BCP with non-contiguous messages. It may be left on at the end of a BOP message (see BOP Receive Operation).
3. RxA is reset relative to the falling edge of RxC after the closing FLAG of a BOP message (REOM = 1 and RxSA active.) or when RxE is dropped.
NOTES:
1. Possible P interrupt requests are: RxDA RxSA TxBE TxU
2. Other SCN2652 status signals and possible uses are S F line idle indicator, frame delimiter. RxA handshake on RxE, line turn around control. TxA handshake on TxE, line turn
3. Line drivers/receivers (LD/LR) convert EIA to TTL voltages and vice-versa.
4. RTS should be dropped after the CRC (BCP) or FLAG (BOP) has been transmitted. This forces CTS low and TxE low.
5. Corresponding high and low order bits of DB must be OR tied.
which resets RxDA and RxSA respectively. For BCP end of message, RxSA may not be set and S/F = 0. The processor should read the last data character and status.
around control.
CLOCK
RESET
(Continued)
RxSA
(8-BIT)
DBEN
RxDA
RxA
RxE
8-BIT
RxC
S/F
P
1
2
3
ADDRESS CONTROL
DATA BUS
SCN2652 MPCC MICROPROCESSOR INTERFACE
READ
DATA
RECEIVE END OF MESSAGE
CONTROL
MODEM
LOGIC
TS BUFFER
A2–A0, R/W DBEN CE
20
“1”
DB0–DB7
READ
STATUS
BYTE
STATUS
SCN2652
DCD
RxE
MPCC
RESET
CTS
TxE
TxC
RxC
TxSO
RxSI
SCN2652/SCN68652
LR
LR
LD
LR
SYNCHRO-
MODEM
NOUS
L
Product specification
) and status (RDSR
RTS, CTS,
DTR, DSR,
DCD
SD00072
SD00073
H
)