scn68652ac2n40 NXP Semiconductors, scn68652ac2n40 Datasheet - Page 3

• Manufacturer Part Number: scn68652ac2n40
• Description: Scn2652/scn68652 Multi-protocol Communications Controller Mpcc
• Manufacturer: NXP Semiconductors

*Indicates possible interrupt signal
Philips Semiconductors
PIN DESCRIPTION
1995 May 1
DB15–DB00
A2–A0
BYTE
CE
R/W
DBEN
RESET
MM
RxE
RxA
RxDA*
RxC
S/F
RxSA*
RxSI
TxE
TxA
TxBE*
TxU*
TxC
TxSO
V
GND
MNEMONIC
Multi-protocol communications controller (MPCC)
CC
PIN NO.
17–10
24–31
19–21
22
18
23
33
40
37
34
35
36
39
38
32
1
8
5
6
2
4
7
3
9
TYPE
I/O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
NAME AND FUNCTION
Data Bus: DB07–DB00 contain bidirectional data while DB15–DB08 contain control and status
information to or from the processor. Corresponding bits of the high and low order bytes can be wire
OR’ed onto an 8-bit bus. The data bus is floating if either CE or DBEN are low.
Address Bus: A2–A0 select internal registers. The four 16-bit registers can be addressed on a word or
byte basis. See Register Address section.
Byte: Single byte (8-bit) data bus transfers are specified when this input is high. A low level specifies
16-bit data bus transfers.
Chip Enable: A high input permits a data bus operation when DBEN is activated.
Read/Write: R/W controls the direction of data bus transfer. When high, the data is to be loaded into the
addressed register. A low input causes the contents of the addressed register to be presented on the
data bus.
Data Bus Enable: After A2–A0, CE, BYTE and R/W are set up, DBEN may be strobed. During a read,
the 3-state data bus (DB) is enabled with information for the processor. During a write, the stable data is
loaded into the addressed register and TxBE will be reset if TDSR was addressed.
Reset: A high level initializes all internal registers (to zero) and timing.
Maintenance Mode: MM internally gates TxSO back to RxSI and TxC to RxC for off line diagnostic
purposes. The RxC and RxSI inputs are disabled and TxSO is high when MM is asserted.
Receiver Enable: A high level input permits the processing of RxSI data. A low level disables the
receiver logic and initializes all receiver registers and timing.
Receiver Active: RxA is asserted when the first data character of a message is ready for the processor.
In the BOP mode this character is the address. The received address must match the secondary station
address if the MPCC is a secondary station. In BCP mode, if strip-SYNC (PCSAR
non-SYNC character is the first data character; if strip-SYNC is zero, the character following the second
SYNC is the first data character. In the BOP mode, the closing FLAG resets RxA. In the BCP mode, RxA
is reset by a low level at RxE.
Receiver Data Available: RxDA is asserted when an assembled character is in RDSR
be presented to the processor. This output is reset when RDSR
Receiver Clock: RxC (1X) provides timing for the receiver logic. The positive going edge shifts serial
data into the RxSR from RxSI.
SYNC/FLAG: S/F is asserted for one RxC clock time when a SYNC or FLAG character is detected.
Receiver Status Available: RxSA is asserted when there is a zero to one transition of any bit in RDSR
except for RSOM. It is cleared when RDSR
Receiver Serial Input: RxSI is the received serial data. Mark = ‘1’, space = ‘0’.
Transmitter Enable: A high level input enables the transmitter data path between TDSR
the end of a message, a low level input causes TxSO = 1(mark) and TxA = 0 after the closing FLAG
(BOP) or last character (BCP) is output on TxSO.
Transmitter Active: TxA is asserted after TSOM (TDSR
when TxE is low and the closing FLAG (BOP) or last character (BCP) has been output on TxSO.
Transmitter Buffer Empty: TxBE is asserted when theTDSR is ready to be loaded with new control
information or data. The processor should respond by loading theTDSR which resets TxBE.
Transmitter Underrun: TxU is asserted during a transmit sequence when the service of TxBE has been
delayed for one character time. This indicates the processor is not keeping up with the transmitter. Line
fill depends on PCSAR
falling edge of TxC.
Transmitter Clock: TxC (1X) provides timing for the transmitter logic. The positive going edge shifts
data out of the TxSR to TxSO.
Transmitter Serial Output: TxSO is the transmitted serial data. Mark = ‘1’, space = ‘0’.
+5V: Power supply.
Ground: 0V reference ground.
11
. TxU is reset by RESET or setting of TSOM (TDSR
3
H
is read.
8
) is set and TxE is raised. This output will reset
L
SCN2652/SCN68652
is read.
8
), synchronized by the
13
) is set, the first
Product specification
L
and is ready to
L
and TxSO. At
H