scn68652 NXP Semiconductors, scn68652 Datasheet
scn68652
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scn68652 Summary of contents
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... SCN2652/SCN68652 Multi-protocol communications controller (MPCC) Product specification IC19 Data Handbook Philips Semiconductors INTEGRATED CIRCUITS 1995 May 01 ...
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... DBEN 17 DB13 18 DB14 22 BYTE 19 DB15 20 R NOTE: DB00 is least significant bit, highest number (that is, DB15, A2) is most significant bit. Figure 1. Pin Configuration 2 Product specification SCN2652/SCN68652 PLCC TOP VIEW Pin Function RxC 25 BYTE RxSI ...
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... CONTROL DBEN S/F RxE RxA RxDA RxSA TxE TxA TxBE TxU 1995 May +5% CC Commercial +70 C SCN2652AC2F40 / SCN68652AC2F40 SCN2652AC2N40 / SCN68652AC2N40 SCN2652AC2A44 / SCN68652AC2A44 PARAMETER BITS PARAMETER CONTROL SYNC/ADDRESS REGISTER 16 RECEIVER DATA/STATUS REGISTER INTERNAL 16 BUS RECEIVER LOGIC AND CONTROL RxC RxSI Figure 2 ...
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... Transmitter Serial Output: TxSO is the transmitted serial data. Mark = ‘1’, space = ‘0’ +5V: Power supply. CC GND 9 I Ground: 0V reference ground. *Indicates possible interrupt signal 1995 May 01 SCN2652/SCN68652 is read read set and TxE is raised. This output will reset 8 . TxU is reset by RESET or setting of TSOM (TDSR 11 4 Product specification ) is set, the first ...
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... NOT DEFINED TGA TABORT TEOM TSOM Figure 3. Short Form Register Bit Formats 5 Product specification SCN2652/SCN68652 DESCRIPTION* and PCR contain parameters common to the contains a programmable BIT PATTERN FUNCTION 01111110 Frame message 11111111 generation Terminate communication 01111111 detection Terminate loop mode ...
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... L TDSAR L TXSR ( TXCRC ACC (16) CRC–16 OR CRC–CCITT 1, 2 SEL CONTROL CHARACTER GENERATOR FLAG ABORT GA Figure 5. MPCC Transmitter Data Path 6 Product specification SCN2652/SCN68652 . TO CRC RDSR L . CRC . CRC M U RxSR ( BOP CRC RERR CRC– COMPARATOR CRC–CCIT = F0B8 ...
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... H When the processor has read the last character of the message, it should drop RxE which disables the receiver logic and initializes all H receiver registers and timing. 7 Product specification SCN2652/SCN68652 each time RxSA is asserted. If RDSR is 9–15 9 should be examined accumulated in 8–10 ...
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... Transmitter operation for BOP is shown in Figure 8. A FLAG is sent after the processor sets the Transmit Start of Message bit (TSOM) and raises TxE. The FLAG is used to synchronize the message that ) is set and TxE 8 follows. TxA will also be asserted. When TxBE is asserted by the 8 Product specification SCN2652/SCN68652 NO L RxE YES ...
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... DB prior to the leading edge of DBEN. The stable data 07–00 is strobed into the addressed register by DBEN. TxBE will be cleared if the addressed register was TDSR 9 Product specification SCN2652/SCN68652 , is generated on each 8–10 when TSOM =0. The processor L are zero. If BYTE = 0, all 16 bits L or RDSR ...
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... READ AND EXAMINE RDSR – ROVRN, H RERR (IF VRC SPECIFIED) RxE = 0 WHEN LAST CHARACTER HAS BEEN SERVICED NOTES: 1. Test made every RxC time. 2. Test made on Rx character boundary. 1995 May 01 SCN2652/SCN68652 INITIALIZE PCSAR, PCR A RxE = 1? NO YES SYNC 1 DETECT NO IN CCSR? YES SYNC ...
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... SERIALIZE DATA CHARACTER IN TxDB, ZERO INSERTION, ACCUMULATE CRC IF SPECIFIED BY ECM, TRANSMIT ON TxSO NO TEOM = 1? YES TRANSMIT ACCUMULATED FCS (IF SPECIFIED) AS INVERTED REMAINDER TRANSMIT FLAG ON TxSO* NO TEOM = 0? YES TSOM YES NO TxE = 0? NO YES A Figure 8. BOP Transmit 11 Product specification SCN2652/SCN68652 FLAG IF IDLE = 1 TSOM = 1? YES B SD00063 ...
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... TxSO = SYNC FROM PCSAR TRANSMIT ACCUMULATED CRC SPECIFIED (IF NO CRC, TEOM SHOULD = 0) NO TxSO = SYNC OR TxDB DEPENDING ON TEOM TxE YES NO TxE = 0? YES A Figure 9. BCP Transmit 12 Product specification SCN2652/SCN68652 A B UNDER- RUN? YES IF IDLE = 0 L MARK IF IDLE = 1 UNTIL TSOM = 1 B IDLE BIT SD00064 ...
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... PCR are not affected during loading. Always 0 when read. Transmitter character length is loaded by the processor when TxCLe = 0. Character bit length specification format is identical to RxCL valid after transmission of single byte address and control fields. 13 Product specification SCN2652/SCN68652 8 Char length (bits ...
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... Determines MPCC Protocol mode PROTO = 0 PROTO = 1 All parties address. If this bit is set, the receiver data path is enabled by an address field of ‘11111111’ as well as the normal secondary station address. 14 Product specification SCN2652/SCN68652 Suggested Mode Char. length BOP 1–8 BCP 8 ––– ...
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... TERR is cleared by setting TSOM. See timing diagram. ABORT’s or FLAG’s are sent as fill characters (IDLE = SYNC’s or MARK’s are sent as fill characters (IDLE = 0 or 1). For IDLE = 1 the last character before underrun is not valid. 15 Product specification SCN2652/SCN68652 , should be CRC–CCITT 8–10 L ...
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... TEST CONDITIONS I = 1.6mA –100 5.25V 5.25V 5.25V OUT 1MHz 0V 1MHz OUT 16 Product specification SCN2652/SCN68652 , reset H : 8– 8–10 LIMITS UNIT UNIT Min Typ Max 0.8 V 2.0 0.4 V 2.4 150 ...
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... RESET AND WRITE DATA BUS DBEN ACS CE, R/W, BYTE t ACS D – FLOATING (READ) D – (WRITE Figure 10. Timing Diagrams 17 Product specification SCN2652/SCN68652 UNIT UNIT Typ Max 170 ns ns 250 150 ns 2.0 MHz ns t DBEN t ACH t ACH NOT VALID VALID FLOATING t ...
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... TRANSMIT – START OF MESSAGE 1 8 TxC 1 SYNC/FLAG LOAD 1st CHAR RESET TSOM and/or TDSR . It is reasserted on the rising edge of the TxC that corresponds to the transmission of the last bit of each H L Figure 12. Timing Diagrams (cont.) 18 Product specification SCN2652/SCN68652 SD00066 1ST CHAR LOAD 2nd CHAR SD00067 ...
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... It goes high one TxC before character transmission begins and also when TxA has been H/L Figure 13. Timing Diagrams (cont.) TRANSMIT TIMING – END OF BCP MESSAGE 1 LAST CHAR CRC SET TEOM RESET TEOM Figure 14. Timing Diagrams (cont.) 19 Product specification SCN2652/SCN68652 FLAG MARK SD00068 MARK SD00069 ...
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... S/F goes high relative to rising edge of RxC anytime a SYNC (BCP) or FLAG (BOP) is detected. 1995 May 01 TRANSMIT UNDERRUN SET TSOM Figure 15. Timing Diagrams (cont.) RECEIVE – START OF MESSAGE 2nd CHAR READY TO BE READ 1st CHAR READ Figure 16. Timing Diagrams (cont.) 20 Product specification SCN2652/SCN68652 SD00070 2nd CHAR READ SD00071 ...
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... Figure 17. Timing Diagrams (cont.) RESET TS BUFFER STATUS DB0–DB7 MPCC SCN2652 A2–A0, R/W DBEN CE “1” BYTE RxE MODEM DCD CONTROL LOGIC Figure 18. Typical Applications 21 Product specification SCN2652/SCN68652 ) and status (RDSR ) L H SD00072 TxC LR RxC LR SYNCHRO- NOUS TxSO MODEM LD RxSI LR RTS, CTS, ...
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... Figure 19. Typical Applications (cont.) CHANNEL INTERFACE BAUD RATE GENERATOR LD LR RxC TxC LR LD MPCC SCN2652 TxSO RxSI LD LR RxSI TxSO Modem – DC Baseband Transmission Figure 20. Typical Applications (cont.) 22 Product specification SCN2652/SCN68652 DATA BUS RxDA R/W TxBE MEMORY ADDRESS, CE, R/W SD00074 RxC COMPUTER MPCC OR TERMINAL SD00075 ...
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... SCN2652/SCN2653 INTERFACE TYPICAL PROTOCOLS: INTERRUPTS CPU 1995 May 01 BISYNC, DDCMP, SDLC, HDLC TxBE, TxU, RxDA, RxSA DB7–DB0 MPCC SCN2652 R/W DBEN CE CE0 A1 R/W A0 CE1 INT (OPEN DRAIN) 5V Figure 21. Typical Applications (cont.) 23 Product specification SCN2652/SCN68652 TxD RxD TxC RxC DB7–DB0 PGC SCN2653 SD00076 ...
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E – PIN # 1 0.100 (2.54) BSC 2.087 (53.01) – D – 2.038 (51.77) 0.070 (1.78) 0.050 (1.27) – T – SEATING PLANE 0.023 (0.58 0.010 (0.254) 0.015 (0.38) NOTES: 0.098 ...
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Philips Semiconductors Multi-protocol communications controller (MPCC) DIP40: plastic dual in-line package; 40 leads (600 mil) 1998 May 01 SCN2652/SCN68562 25 Product specification SOT129-1 ...
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Philips Semiconductors Multi-protocol communications controller (MPCC) PLCC44: plastic leaded chip carrier; 44 leads 1998 May 01 SCN2652/SCN68562 26 Product specification SOT187-2 ...
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Philips Semiconductors Multi-protocol communications controller (MPCC) 1998 May 01 SCN2652/SCN68562 NOTES 27 Product specification ...
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Philips Semiconductors Multi-protocol communications controller (MPCC) Data sheet status Data sheet Product Definition status status Objective Development This data sheet contains the design target or goal specifications for product development. specification Specification may change in any manner without notice. Preliminary ...