scn68652 NXP Semiconductors, scn68652 Datasheet - Page 9

• Manufacturer Part Number: scn68652
• Description: Multi-protocol Communications Controller Mpcc
• Manufacturer: NXP Semiconductors

Philips Semiconductors
MPCC, the processor should load TDSR
the message. TSOM should be cleared at the same time TDSR
loaded (16-bit data bus) or immediately thereafter (8-bit data bus).
FLAGS are sent as long as TSOM = 1. For counting the number of
FLAGs, the processor should reassert TSOM in response to the
assertion of TxBE.All succeeding characters are loaded into TDSR
by the processor when TxBE = 1. Each
character is serialized in TxSR and transmitted on TxSO. Internal
zero insertion logic stuffs a “0” into the serial bit stream after five
successive “1s” are sent. This insures a data character will not
match a FLAG, ABORT, or GA reserved control character. As each
character is transmitted, the Frame Check Sequence (FCS) is
generated as specified by Error Control Mode (PCSAR
FCS should be the CRC–CCITT polynomial (X
preset to 1s. If an underrun occurs (processor is not keeping up with
the transmitter), TxU and TERR (TDSR
ABORT or FLAG used as the TxSO line fill depending on the state
of IDLE (PCSAR
underrun condition. To retransmit the message, the processor
should proceed with the normal start of message sequence.
A residual character of 1 to 7 bits may be transmitted at the end of
the information field. In response to TxBE, write the residual
character length into TxCL and load TxDB with the residual
character. Dynamic alteration of character length should be done in
exactly the same sequence. The character length will be changed
on the next transmit character boundary.
After the last data character has been loaded into TDSR
to TxSR (TxBE = 1), the processor should set TEOM (TDSR
MPCC will finish transmitting the last character followed by the FCS
and the closing FLAG. The processor should clear TEOM and drop
TxE when the next TxBE is asserted. This corresponds to the start
of closing FLAG transmission. When TxE has been dropped. TxA
will be low 1 1/2 bit times after the last bit of the closing FLAG has
been transmitted. TxSO will be marked after the closing FLAG has
been transmitted.
If TxE and TEOM are high, the transmitter continues to send
FLAGs. The processor may initiate the next message by resetting
TEOM and setting TSOM, or by loading TDSR
character and then simply resetting TSOM (without setting TSOM).
TxBCP Operation
Transmitter operation for BCP mode is shown in Figure 9. TxA will
be asserted after TSOM = 1 and TxE is raised. At that time SYNC
characters are sent from PCSAR
as TSOM = 1. TxBE is asserted at the start of transmission of the
first SYNC character. For counting the number of SYNCs, the
processor should reassert TSOM in response to the assertion of
TxBE. When TSOM = 0 transmission is from TDSR
loaded with characters from the processor each time TxBE is
asserted. If this loading is delayed for more than one character time,
an underrun results: TxU and TERR are asserted and the
TxSO line fill depend on IDLE (PCSAR
TSOM and retransmit the message to recover. This is not
compatible with IBM’s BISYNC, so that the user must not underrun
when supporting that protocol.
1995 May 01
Multi-protocol communications controller (MPCC)
11
). The processor must set TSOM to reset the
L
or TDSR
11
15
L
). The processor must set
) will be asserted with
with the first character of
L
(IDLE = 0 or 1) as long
16
L
with a data
+ X
L
, which must be
12
+ X
8–10
L
and sent
5
). The
9
+ 1)
). The
L
is
L
9
The default value for all registers is zero. This corresponds to BOP,
CRC–16, if specified by PCSAR
character transmitted from TDSR
must set TEOM = 1 after the last data character has been sent to
TxSR (TxBE = 1). The MPCC will finish transmitting the last data
character and the CRC–16 field before sending SYNC characters
which are transmitted as long as TEOM = 1. If SYNCs are not
desired after CRC–16 transmission, the processor should clear
TEOM and lower TxE when the TxBE corresponding to the start of
CRC–16 transmission is asserted. When TEOM = 0, the line is
marked and a new message may be initiated by setting TSOM and
raising TxE.
If VRC is specified, it is generated on each data character and the
data character length must not exceed 7 bits. For software LRC or
CRC, TEOM should be set only if SYNC’s are required at the end of
the message block.
SPECIAL CASE: The capability to transmit 16 spaces is provided
for line turnaround in half duplex mode or for a control recovery
situation. This is achieved by setting TSOM and TEOM, clearing
TEOM when TxBE = 1, and proceeding as required.
PROGRAMMING
Prior to initiating data transmission or reception, PCSAR and PCR
must be loaded with control information from the processor. The
contents of these registers (see Register Format section) will
configure the MPCC for the user’s specific data communication
environment. These registers should be loaded during power-on
initialization and after a reset operation. They can be changed at any
time that the respective transmitter or receiver is disabled.
primary station mode, 8-bit character length, FCS = CRC–CCITT
preset to 1s.
For BOP mode the character length register (PCR) may be set to
the desired values during system initialization. The address and
control fields will automatically be 8-bits. If a residual character is to
be transmitted, TxCL should be changed to the residual character
length prior to transmission of that character.
DATA BUS CONTROL
The processor must set up the MPCC register address (A2–A0),
chip enable (CE), byte select (BYTE), and read/write (R/W) inputs
before each data bus transfer operation.
During a read operation (R/W = 0), the leading edge of DBEN will
initiate an MPCC read cycle. The addressed register will place its
contents on the data bus. If BYTE = 1, the 8-bit byte is placed on
DB15–08 or DB07–00 depending on the H/L status of the register
addressed. Unused bits in RDSR
(DB15–00) contain MPCC information. The trailing edge of DBEN
will reset RxDA and/or RxSA if RDSR
respectively.
DBEN acts as the enable and strobe so that the MPCC will not
begin its internal read cycle until DBEN is asserted.
During a write operation (R/W = 1), data must be stable on DB
and/or DB
is strobed into the addressed register by DBEN. TxBE will be
cleared if the addressed register was TDSR
07–00
prior to the leading edge of DBEN. The stable data
SCN2652/SCN68652
8–10
L
L
when TSOM =0. The processor
are zero. If BYTE = 0, all 16 bits
, is generated on each
L
or RDSR
H
or TDSR
Product specification
H
is addressed
L
.
15–08