hi-3583a Holt Integrated Circuits, Inc., hi-3583a Datasheet

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hi-3583a

Manufacturer Part Number
hi-3583a
Description
3.3v Terminal Ic With High-speed Interface
Manufacturer
Holt Integrated Circuits, Inc.
Datasheet
FEATURES
GENERAL DESCRIPTION
The HI-3582A/HI-3583A from Holt Integrated Circuits are
silicon gate CMOS devices for interfacing a 16-bit parallel
data bus directly to the ARINC 429 serial bus. The
HI-3582A/HI-3583A design offers a high-speed host CPU
interface compared with the earlier HI-3582/HI-3583
products. The device provides two receivers each with
label recognition, 32 by 32 FIFO, and analog line receiver.
Up to 16 labels may be programmed for each receiver.
The independent transmitter has a 32 X 32 FIFO and a
built-in line driver. The status of all three FIFOs can be
monitored using the external status pins, or by polling the
HI-3582A/HI-3583A status register. Other features include
a programmable option of data or parity in the 32nd bit,
and the ability to unscramble the 32 bit word.
versions
resistance and output resistance to allow users to more
easily add external lightning protection circuitry.
The 16-bit parallel data bus exchanges the 32-bit ARINC
data word in two steps when either loading the transmitter
or interrogating the receivers. The databus and all control
signals are 3.3V CMOS compatible.
The HI-3582A/HI-3583A apply the ARINC protocol to the
receivers and transmitter. Timing is based on a 1 Mega-
hertz clock.
(DS3582A Rev. New)
(
February 2009
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ARINC specification 429 compatible
High-speed 3.3V logic interface
Dual receiver and transmitter interface
Analog line driver and receivers connect
directly to ARINC bus
Programmable label recognition
On-chip 16 label memory for each receiver
32 x 32 FIFOs each receiver and transmitter
Independent data rate selection for
Transmitter and each receiver
Status register
Data scramble control
32nd transmit bit can be data or parity
Self test mode
Low power
Industrial & extended temperature ranges
are available with different values of input
HOLT INTEGRATED CIRCUITS
3.3V Terminal IC with High-Speed Interface
HI-3582A, HI-3583A
Also,
www.holtic.com
PIN CONFIGURATIONS
(See page 14 for additional pin configuration)
APPLICATIONS
BD15 - 9
BD14 - 10
BD12 - 12
BD13 - 11
BD11 - 13
D/R2
(Note: All 3 VDD pins
EN1
EN2
HF1
HF2
SEL - 6
FF1
FF2
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Avionics data communication
Serial to parallel conversion
Parallel to serial conversion
- 1
- 2
- 3
- 4
- 5
- 7
- 8
52 - Pin Plastic Quad Flat Pack (PQFP)
BD15 - 12
BD14 - 13
BD13 - 14
BD12 - 15
BD11 - 16
D/R1
D/R2
SEL - 8
N/C - 1
EN1
EN2
HF1
HF2
FF1
FF2
N/C - 11
64 - Pin Plastic 9mm x 9mm
- 2
- 3
- 4
- 5
- 6
- 7
- 9
- 10
Chip-Scale Package
must
HI-3582APQM
HI-3583APQM
HI-3582APQT
HI-3583APQT
HI-3582APQI
HI-3583APQI
HI-3582APCM
HI-3583APCM
HI-3582APCT
HI-3583APCT
HI-3582APCI
HI-3583APCI
be connected to the same 3.3V supply)
&
&
See Note below
ARINC 429
48
47
46 - N/C
45 - V+
44 - TXBOUT
43 - TXAOUT
42 - V-
41
40 -
39 -
38 - TX/R
37 -
36 -
35 -
34 - BD01
33 - N/C
(Top View)
-
- ENTX
- N/C
CWSTR
FFT
HFT
PL2
PL1
BD00
39 - N/C
38 -
37 - ENTX
36 - V+
35 - TXBOUT
34 - TXAOUT
33 - V-
32 -
31 -
30 - TX/R
29 -
28 -
27 - BD00
CWSTR
FFT
HFT
PL2
PL1
02/09

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hi-3583a Summary of contents

Page 1

... The 16-bit parallel data bus exchanges the 32-bit ARINC data word in two steps when either loading the transmitter or interrogating the receivers. The databus and all control signals are 3.3V CMOS compatible. The HI-3582A/HI-3583A apply the ARINC protocol to the receivers and transmitter. Timing is based Mega- hertz clock. FEATURES ...

Page 2

... INPUT CLK INPUT TX CLK OUTPUT MR INPUT TEST INPUT HI-3582A, HI-3583A DESCRIPTION +3.3V power supply pin ARINC receiver 1 positive input ARINC receiver 1 negative input ARINC receiver 2 positive input ARINC receiver 2 negative input Receiver 1 data ready flag FIFO full Receiver 1 FIFO Half full, Receiver 1 ...

Page 3

... FUNCTIONAL DESCRIPTION CONTROL WORD REGISTER The HI-3582A/HI-3583A contain a 16-bit control register which is used to configure the device. The control register bits CR0 - CR15 are loaded from BD00 - BD15 when CWSTR control register contents are output on the databus when SEL = 1 and RSR is pulsed low ...

Page 4

... FUNCTIONAL DESCRIPTION (cont.) ARINC 429 DATA FORMAT Control register bit CR15 is used to control how individual bits in the received or transmitted ARINC word are mapped to the HI-3582A/ HI-3583A data bus during data read or write operations. The following table describes this mapping: BYTE 1 DATA ...

Page 5

... D/R FIFO LOAD CONTROL / LABEL / CONTROL DECODE BIT COMPARE LABEL MEMORY EOS ONES SHIFT REGISTER NULL SHIFT REGISTER SHIFT REGISTER ZEROS HI-3582A, HI-3583A CR2(3) ARINC word CR6(9) ARINC word matches label Yes Yes Yes TO PINS CONTROL ...

Page 6

... HI-3582A/HI-3583A status register bits. LABEL RECOGNITION The chip compares the incoming label to the stored labels if label recognition is enabled ...

Page 7

... Timing Diagrams section. HI-3582A-15 and HI-3583A-15 The HI-3582A-15/HI-3583A-15 options are similar to the HI-3582A/ HI-3583A with the exception that they allow an external 15 Kohm resistor to be added in series with each ARINC input without affect- ing the ARINC input thresholds. This option is especially useful in applications where lightning protection circuitry is also required ...

Page 8

... BIT 31 BIT 32 D D/R DON'T CARE SEL EN DATA BUS t ENDATA DATA BUS PL1 PL2 TX/R, FFT HFT DATA BUS CWSTR HI-3582A, HI-3583A DATA RATE - EXAMPLE PATTERN DATA DATA NULL NULL BIT 32 BIT 31 RECEIVER OPERATION t t SELEN t SELEN ENSEL t t ENEN D/REN t DATAEN ...

Page 9

... PL t CWSTR CWSTR EN1 or EN2 t CWHLD t CWSET DATA BUS Set CR1=1 Label #1 t ENDATA HI-3582A, HI-3583A STATUS REGISTER READ CYCLE DON'T CARE t SELEN DATA VALID t ENDATA CONTROL REGISTER READ CYCLE DON'T CARE t SELEN DATA VALID t ENDATA LABEL MEMORY LOAD SEQUENCE Label #2 ...

Page 10

... TXBOUT) 10% one level RIN BIT 32 D D/R D/REN EN t SELEN SEL DON'T CARE t ENPL PL1 PL2 TXR ENTX TXAOUT TXBOUT HI-3582A, HI-3583A TRANSMITTING DATA ARINC BIT ARINC BIT DATA DATA BIT 2 BIT 1 +5V -5V +5V - +10V 90 10% rx 90% ...

Page 11

... Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. HEAT SINK - CHIP-SCALE PACKAGE ONLY The HI-3582APCI/T/M and HI-3583APCI/T/M use a 64-pin plastic chip-scale package. This package has a metal heat sink pad on its bottom surface. This heat sink is electrically connected to the die ...

Page 12

... Output Voltage: Logic "1" Output Voltage Logic "0" Output Voltage Output Current: (All Outputs & Bi-directional Pins) Output Capacitance: Operating Voltage Range Operating Supply Current VDD V+ V- HI-3582A, HI-3583A CONDITIONS SYMBOL ONE V Common mode voltages IH ZERO V less than ±4V with IL ...

Page 13

... Line driver transition differential times: (High Speed, control register CR13 = Logic 0) (Low Speed, control register CR13 = Logic 1) REPEATER OPERATION TIMING Delay - TX/R LOW to ENTX HIGH MASTER RESET PULSE WIDTH ARINC DATA RATE AND BIT TIMING HI-3582A, HI-3583A + SYMBOL Pulse Width - CWSTR t CWSTR ...

Page 14

... ADDITIONAL HI-3582A / HI-3583A PIN CONFIGURATIONS BD15 - 16 BD14 - 17 BD13 - 18 BD12 - 19 BD11 - 20 ORDERING INFORMATION HI - 358xA PART NUMBER No dash number PART NUMBER PART NUMBER PART NUMBER PART NUMBER HI-3582A, HI-3583A FF1 - 8 HF1 - 9 D/ HI-3582ACJI FF2 - 11 HI-3582ACJT HF2 - 12 HI-3582ACJM SEL - 13 & EN1 - 14 EN2 ...

Page 15

... REVISION HISTORY Revision Date Page Description of Change DS3582A,Rev. New 02/12/09 HI-3582A, HI-3583A New document HOLT INTEGRATED CIRCUITS 15 ...

Page 16

... HI-3582A / HI-3583A PACKAGE DIMENSIONS 52-PIN J-LEAD CERQUAD 7 8 .019 .002 (.483 .051) 52-PIN PLASTIC QUAD FLAT PACK (PQFP) .520 BSC SQ (13.2) .063 (1.6) See Detail A .063 MAX. (1.6) BSC = “Basic Spacing between Centers” is theoretical true position dimension and has no tolerance. (JEDEC Standard 95) ...

Page 17

... HI-3582A / HI-3583A PACKAGE DIMENSIONS 64-PIN PLASTIC CHIP-SCALE PACKAGE .354 BSC (9.00) .354 Top View BSC (9.00) .039 max (1.00) Heat sink pad on bottom of package. Heat sink can float or can be connected to V-. DO NOT connect heat sink to VDD, GND or V+ .281 ± .006 (7.15 ± .15 ) .016 ± .004 (0.40 ± ...

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