hi-3593 Holt Integrated Circuits, Inc., hi-3593 Datasheet
hi-3593
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hi-3593 Summary of contents
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... February 2011 GENERAL DESCRIPTION The HI-3593 from Holt Integrated Circuits is a CMOS integrated circuit for interfacing a Serial Peripheral Interface (SPI) enabled microcontroller to the ARINC 429 serial bus. The device provides two receivers, each with user-programmable label recognition for any combination of 256 possible labels Receive FIFO, 3 priority- label quick-access double-buffered registers and analog line receiver ...
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... Receiver 2 Receiver 1 Receive Status RIN2A RIN2B RIN2B-40 ARINC 429 RIN2A-40 Line Receiver 40 KW RIN1A 40 KW RIN1B RIN1B-40 RIN1A-40 HI-3593 VDD (3.3V) Transmitter ARINC 429 Transmit Data FIFO Transmit Status Transmit Control 3.3V Label Receive Control Filter Bit Map Memory ARINC 429 ARINC 429 ...
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... SO pin after the last op code bit is clocked into the decoder, at the next falling SCK edge write instructions, the data field bit-length varies with read instruction type. HI-3593 DESCRIPTION SPI Instructions are of a common format. The first bit specifies whether the instruction is a write “ ...
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... Read Receiver 2 Priority-Label Register #2, ARINC429 bytes 2,3 & 4 (bits 9 - 32) 0xCC R 3 Read Receiver 2 Priority-Label Register #3, ARINC429 bytes 2,3 & 4 (bits 9 - 32) 0xD0 R 1 Read Flag / Interrupt Assignment Register 0xD4 R 1 Read ACLK Division Register 0xFF R 0 Instruction not implemented. No operation. HI-3593 TABLE 1. DEFINED INSTRUCTIONS DESCRIPTION HOLT INTEGRATED CIRCUITS 4 ...
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... Setting SELFTEST causes an internal connection to be made looping-back the transmitter outputs to both receiver inputs for self-test purposes. When in self-test mode, the HI-3593 ignores data received on the two ARINC 429 receive channels and holds the on-chip line driver outputs in the NULL state to prevent self-test data being transmitted to other receivers on the bus. If the TPARITY bit is set, the transmitter inserts an odd parity bit if ODDEVEN = “ ...
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... Default Description 7 X R/W 0 Not used R/W 0 Not used R/W 0 Not used DIV[3:0] R/W 0 The value programmed in DIV[3:0] sets the ACLK division ratio (see table R/W 0 Not used. HI-3593 MSB MSB 0 ...
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... The value of R2FLAG[1:0] defines the function of the R2FLAG output pin, as follows: 3-2 R1INT[1:0] R/W 0 The value of R1INT[1:0] defines the function of the R1INT output pin, as follows: 1-0 R1FLAG[1:0] R/W 0 The value of R1FLAG[1:0] defines the function of the R1FLAG output pin, as follows: HI-3593 MSB 00 R2INT pulses high when a valid message is received and ...
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... Conversely, the data field MSB is bit 31. So the bit significance of the label byte and data fields are opposite. The HI-3593 may be programmed to “flip” the bit ordering of the label byte as soon received and immediately prior to transmission. This is accomplished by setting the TFLIP bit to a “1” ...
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... CLOCK FREQUENCY SELECTION For correct ARINC 429 data rate transmission and reception, and bit timing, the HI-3593 transmit and receive logic requires a 1 MHz +/- 1% reference clock source. The clock is input at the ACLK pin and must be 1 MHz or any even multiple of 1 MHz MHz clock source greater than 1 MHz is used, then the ACLK Division Register must be programmed with the appropriate scaling value ...
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... RECEIVED DATA ACCEPTANCE AND STORAGE The HI-3593 subjects incoming ARINC 429 messages to three different data filter checks before data is accepted. First all words are filtered for matching S/D bits, if enabled. Secondly, the word label ...
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... Table 3. defines the rules for Receive FIFO loading. READING THE LABEL LOOK-UP TABLE The contents of the Label Look-up table may be read via the SPI interface using Op-Code 0x98 (Receiver 1) or 0xB8 (Receiver 2) as described in Table 1. HI-3593 PARITY CHECK WORD GAP WORD GAP ...
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... Recommended values are given in the block diagram on page 2. LINE DRIVER OPERATION The line driver in the HI-3593 directly drives the ARINC 429 bus. The two ARINC 429 outputs (TXAOUT and TXBOUT) provide a differential voltage to produce a +10V One, a -10V Zero, and a 0 Volt Null ...
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... LINE RECEIVER INPUT PINS The HI-3593 has two sets of Line Receiver input pins for each of the two receivers, RINxA/B and RINxA/B-40. Only one pair may be used to connect to the ARINC 429 bus. The unused pair must be left floating ...
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... SERIAL PERIPHERAL INTERFACE SERIAL PERIPHERAL INTERFACE (SPI) BASICS The HI-3593 uses an SPI synchronous serial interface for host access to internal registers and data FIFOs. Host serial communication is enabled through the Chip Select ( CS ) pin, and is accessed via a three-wire interface consisting of Serial Data Input (SI) from the host, Serial Data Output (SO) to the host and Serial Clock (SCK) ...
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... HOST SERIAL PERIPHERAL INTERFACE, cont. HI-3593 SPI COMMANDS For the HI-3593, each SPI read or write operation begins with an 8-bit command byte transferred from the host to the device after assertion Since HI-3593 command byte reception is half-duplex, the host discards the dummy byte it receives while serially transmitting the command byte ...
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... DATA NULL BIT 30 ARINC DATA BIT 31 BIT 32 FLAGS (1) R1INT / R2INT t RFLG (1) Receiver status flag outputs: R1FLAG, R2FLAG, MB1-1, MB1-2, MB1-3, MB2-1, MB2-2, MB2-3 HI-3593 SERIAL INPUT TIMING DIAGRAM t CYC t t CES CES t t SCKR DH MSB SERIAL OUTPUT TIMING DIAGRAM ...
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... TIMING DIAGRAMS (cont.) AOUT BOUT V DIFF (AOUT - BOUT) one level CS SPI INSTRUCTION 0x0C SI TEMPTY / TFULL t TFLG AOUT BOUT HI-3593 OUTPUT WAVEFORMS ARINC BIT ARINC BIT DATA DATA BIT 2 BIT 1 +5V -5V +5V - +10V 90 10% t 10% rx 90% zero level -10V TRANSMITTING DATA ...
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... HEAT SINK - CHIP-SCALE PACKAGE ONLY The HI-3593PCx uses a 44-pin plastic chip-scale package. This package has a metal heat sink pad on its bottom surface. This heat sink is electrically isolated from the die. To enhance thermal dissipation, the heat sink can be ABSOLUTE MAXIMUM RATINGS Supply Voltages V ...
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... Output Voltage: Logic "1" Output Voltage Logic "0" Output Voltage Output Current: Output Capacitance: OPERATING VOLTAGE RANGE OPERATING SUPPLY CURRENT Transmitting Data in High-Speed Mode. Transmitting Data in High-Speed Mode. HI-3593 CONDITIONS SYMBOL ONE V Common mode voltages IH ZERO V less than ±25V with ...
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... FIFO Flag delay after enable transmit instruction - Hi Speed FIFO Flag delay to ARINC 429 data output - Hi Speed FIFO Flag delay to ARINC 429 data output - Lo Speed Line driver transition differential times: High Speed Low Speed HI-3593 + SYMBOL SCK clock period active after last SCK rising edge inactive between SPI instructions ...
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... ORDERING INFORMATION HI - 3593 PART NUMBER PART NUMBER PART NUMBER HI-3593 LEAD FINISH Blank Tin / Lead (Sn / Pb) Solder 100% Matte Tin (Pb-free, RoHS compliant) F TEMPERATURE RANGE I -40°C TO +85°C T -55°C TO +125°C M -55°C TO +125°C PACKAGE DESCRIPTION PC 44 PIN PLASTIC CHIP-SCALE, QFN (44PCS) ...
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... REVISION HISTORY Revision Date Description of Change DS3593,Rev. New 2/3/11 Initial Release. HI-3593 HOLT INTEGRATED CIRCUITS 22 ...
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... SQ. See Detail A .063 MAX. (1.6) BSC = “Basic Spacing between Centers” is theoretical true position dimension and has no tolerance. (JEDEC Standard 95) HI-3593 PACKAGE DIMENSIONS .203 ± .006 (5.15 ± .15) .008 typ (0.2) .394 ± .004 (10.0 ± .10) SQ. .055 .002 ± ...