oq2541u NXP Semiconductors, oq2541u Datasheet - Page 7

• Manufacturer Part Number: oq2541u
• Description: Sdh/sonet Data And Clock Recovery Unit Stm1/4/16 Oc3/12/48 Ge
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Power supply and power control loop
The OQ2541 contains an on-board voltage regulator.
An external power transistor is needed to deliver the
supply to this circuit. The required external circuit is
straightforward, and can be built using a few components.
A suitable circuit with a power supply of 4.5 V is illustrated
in Fig.6.
A different configuration could be used, as long as the
power supply rejection ratio is greater than 60 dB for all
frequencies. The inductor is a RF choke with an
impedance greater than 50
2 MHz. Any transistor with a
sink capability can be used.
The OQ2541 can also be used with a power supply of
power control circuit is to change the emitter resistor R1
(see Table 1).
Table 1 Value of resistor R1.
1999 May 27
5.0 or 5.2 V. The only adaptation to be made to the
CREF
SDH/SONET data and clock recovery unit
STM1/4/16 OC3/12/48 GE
DIN,
V EE
POWER SUPPLY
Fig.4 RF data and clock input circuit.
4.5 V
5.0 V
5.2 V
50
at frequencies higher than
> 100 and enough current
RESISTOR R1
2.0
6.8
8.2
MGL669
50
DINQ,
CREFQ
7
Output amplitude reference
The voltage swing at the CML compatible output stages
(pins DOUT, DOUTQ, COUT, COUTQ, DLOOP,
DLOOPQ, CLOOP and CLOOPQ) can be controlled by
adjusting the voltage on pin AREF (see Fig.7). An internal
voltage divider of 500
ground and V
In most applications the outputs will be DC-coupled to a
load of 50 . The output level regulation circuit will
maintain a 200 mV (p-p) single-ended swing across this
load. The voltage on pin AREF is half the single-ended
peak-to-peak value of the output signal ( 100 mV).
No adjustments are necessary with DC-coupling.
If the outputs are AC-coupled, the voltage on pin AREF is
half the single-ended peak-to-peak value of the output
signal multiplied by a factor
where R
impedance of the OQ2541 (100 ).
handbook, halfpage
L
Fig.5 RF data and clock output circuit.
is the external load and R
EE
100
initially fixes this level.
V EE
OQ2541HP; OQ2541U
and 16 k connected between
R
------------------- -
L
R
+
100
V AREF
L
R
o
DOUTQ, COUTQ
o
DOUT, COUT
Product specification
is the output
MGL670