am41dl16x4d Meet Spansion Inc., am41dl16x4d Datasheet - Page 4

• Manufacturer Part Number: am41dl16x4d
• Description: Stacked Multi-chip Package Mcp Flash Memory And Sram Am29dl16xd 16 Megabit 2 M X 8-bit/1 M X 16-bit Cmos 3.0 Volt-only, Simultaneous Operation Flash Memory And 4 Mbit 512 K X 8-bit/256 K X 16-bit Static Ram
• Manufacturer: Meet Spansion Inc.

TABLE OF CONTENTS
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 5
MCP Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . 5
Flash Memory Block Diagram. . . . . . . . . . . . . . . . 6
Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . 7
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 9
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . 10
Common Flash Memory Interface (CFI) . . . . . . . 23
Command Definitions . . . . . . . . . . . . . . . . . . . . . . 26
Special Handling Instructions for FBGA Package .................... 7
Word/Byte Configuration ....................................................... 15
Requirements for Reading Array Data ................................... 15
Writing Commands/Command Sequences ............................ 15
Simultaneous Read/Write Operations with Zero Latency ....... 15
Standby Mode ........................................................................ 16
Automatic Sleep Mode ........................................................... 16
RESET#: Hardware Reset Pin ............................................... 16
Output Disable Mode .............................................................. 16
Autoselect Mode ..................................................................... 19
Write Protect (WP#) ................................................................ 19
Temporary Sector/Sector Block Unprotect ............................. 20
SecSi (Secured Silicon) Sector Flash Memory Region .......... 22
Hardware Data Protection ...................................................... 22
Table 1. Device Bus Operations—Flash Word Mode, CIOf = V
SRAM Word Mode, CIOs = V
Table 2. Device Bus Operations—Flash Word Mode, CIOf = V
SRAM Byte Mode, CIOs = V
Table 3. Device Bus Operations—Flash Byte Mode, CIOf = V
SRAM Word Mode, CIOs = V
Table 4. Device Bus Operations—Flash Byte Mode, CIOf = V
Byte Mode, CIOs = V
Accelerated Program Operation .......................................... 15
Autoselect Functions ........................................................... 15
Table 5. Device Bank Division ........................................................16
Table 6. Sector Addresses for Top Boot Sector Devices ............... 17
Table 7. SecSi Sector Addresses for Top Boot Devices ................17
Table 8. Sector Addresses for Bottom Boot Sector Devices ...........18
Table 9. SecSi
Table 10. Top Boot Sector/Sector Block Addresses for Protection/Un-
protection ........................................................................................19
Table 11. Bottom Boot Sector/Sector Block Addresses
for Protection/Unprotection .............................................................19
Figure 1. Temporary Sector Unprotect Operation........................... 20
Figure 2. In-System Sector/Sector Block Protect and Unprotect Algo-
rithms .............................................................................................. 21
Factory Locked: SecSi Sector Programmed and Protected At
the Factory .......................................................................... 22
Customer Lockable: SecSi Sector NOT Programmed or Pro-
tected At the Factory ........................................................... 22
Low V
Write Pulse “Glitch” Protection ............................................ 23
Logical Inhibit ...................................................................... 23
Power-Up Write Inhibit ......................................................... 23
Table 12. CFI Query Identification String........................................ 23
System Interface String................................................................... 24
Table 14. Device Geometry Definition ............................................ 24
Table 15. Primary Vendor-Specific Extended Query ...................... 25
CC
Write Inhibit ........................................................... 22
Addresses for Bottom Boot Devices ..................18
SS
..................................................................14
SS
CC
CC
..................................................... 11
......................................................12
.....................................................13
P R E L I M I N A R Y
IL
SS
; SRAM
IH
IH
Am41DL16x4D
;
;
;
Write Operation Status . . . . . . . . . . . . . . . . . . . . 32
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 36
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . 36
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 37
SRAM DC and Operating Characteristics . . . . . 38
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Key To Switching Waveforms . . . . . . . . . . . . . . . 40
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 41
Reading Array Data ................................................................ 26
Reset Command ..................................................................... 26
Autoselect Command Sequence ............................................ 26
Enter SecSi Sector/Exit SecSi Sector Command Sequence .. 27
Byte/Word Program Command Sequence ............................. 27
Chip Erase Command Sequence ........................................... 28
Sector Erase Command Sequence ........................................ 28
Erase Suspend/Erase Resume Commands ........................... 29
DQ7: Data# Polling ................................................................. 32
RY/BY#: Ready/Busy# ............................................................ 33
DQ6: Toggle Bit I .................................................................... 33
DQ2: Toggle Bit II ................................................................... 34
Reading Toggle Bits DQ6/DQ2 ............................................... 34
DQ5: Exceeded Timing Limits ................................................ 34
DQ3: Sector Erase Timer ....................................................... 34
CMOS Compatible .................................................................. 37
Zero-Power Flash ................................................................. 39
SRAM CE#s Timing ................................................................ 41
Flash Read-Only Operations ................................................. 42
Hardware Reset (RESET#) .................................................... 43
Flash Word/Byte Configuration (CIOf) .................................... 44
Flash Erase and Program Operations .................................... 45
Unlock Bypass Command Sequence .................................. 27
Figure 3. Program Operation ......................................................... 28
Figure 4. Erase Operation.............................................................. 29
Table 16. Command Definitions (Flash Word Mode) ...................... 30
Table 17. Autoselect Device IDs (Word Mode) .............................. 30
Table 18. Command Definitions (Flash Byte Mode) ....................... 31
Table 19. Autoselect Device IDs (Byte Mode) ............................... 31
Figure 5. Data# Polling Algorithm .................................................. 32
Figure 6. Toggle Bit Algorithm........................................................ 33
Table 20. Write Operation Status ................................................... 35
Industrial (I) Devices ............................................................ 36
V
Figure 9. I
Currents) ........................................................................................ 39
Figure 10. Typical I
Figure 11. Test Setup.................................................................... 40
Table 21. Test Specifications ......................................................... 40
Figure 12. Input Waveforms and Measurement Levels ................. 40
Figure 13. Timing Diagram for Alternating Between
SRAM to Flash ............................................................................... 41
Figure 14. Read Operation Timings ............................................... 42
Figure 15. Reset Timings ............................................................... 43
Figure 16. CIOf Timings for Read Operations................................ 44
Figure 17. CIOf Timings for Write Operations................................ 44
Figure 18. Program Operation Timings.......................................... 46
Figure 19. Accelerated Program Timing Diagram.......................... 46
Figure 20. Chip/Sector Erase Operation Timings .......................... 47
Figure 21. Back-to-back Read/Write Cycle Timings ...................... 48
CC
f/V
CC
s Supply Voltage ................................................... 36
CC1
Current vs. Time (Showing Active and Automatic Sleep
CC1
vs. Frequency ............................................ 39
3