th50vsf3582 TOSHIBA Semiconductor CORPORATION, th50vsf3582 Datasheet - Page 43
th50vsf3582
Manufacturer Part Number
th50vsf3582
Description
Sram And Flash Memory Mixed Multi-chip Package
Manufacturer
TOSHIBA Semiconductor CORPORATION
Datasheet
1.TH50VSF3582.pdf
(50 pages)
- Current page: 43 of 50
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Notes:
TIMING FOR SWITCHING BETWEEN FLASH AND SRAM MODES
(1)
(2)
(3)
(4)
(5)
(6)
If
remain High-Impedance.
If
remain High-Impedance.
If OE is High during a Write cycle, the outputs will remain High-Impedance.
Because I/O pins may be in Output state at this point, input signals of the opposite value must not be
applied.
D
WE remains High during a Read cycle.
OUT
CE2S
CE
CE
CE
CEF
1
S
1
1
6 stops toggling when the last command has been completed.
S
S
goes Low (or CE2S goes High) at the same time as or after WE goes Low, the outputs will
goes High (or CE2S goes Low) at the same time as or before WE goes High, the outputs will
t
CCR
TH50VSF3582/3583AASB
2001-06-08 43/50
t
CCR
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