k4t1g084qe Samsung Semiconductor, Inc., k4t1g084qe Datasheet - Page 17

• Manufacturer Part Number: k4t1g084qe
• Description: 1gb E-die Ddr2 Sdram
• Manufacturer: Samsung Semiconductor, Inc.

Note :
1. IDD specifications are tested after the device is properly initialized
2. Input slew rate is specified by AC Parametric Test Condition
3. IDD parameters are specified with ODT disabled.
4. Data bus consists of DQ, DM, DQS, DQS, RDQS, RDQS, LDQS, LDQS, UDQS, and UDQS. IDD values must be met with all combinations of EMRS
5. Definitions for IDD
For purposes of IDD testing, the following parameters are utilized
Detailed IDD7
The detailed timings are shown below for IDD7.
Legend: A = Active; RA = Read with Autoprecharge; D = Deselect
IDD7: Operating Current: All Bank Interleave Read operation
All banks are being interleaved at minimum tRC(IDD) without violating tRRD(IDD) and tFAW(IDD) using a burst length of 4. Control and address bus
inputs are STABLE during DESELECTs. IOUT = 0mA
Timing Patterns for 8bank devices x4/ x8
-DDR2-667 5/5/5 : A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D A4 RA4 D A5 RA5 D A6 RA6 D A7 RA7 D D
-DDR2-800 6/6/6 : A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D D A4 RA4 D A5 RA5 D A6 RA6 D A7 RA7 D D D
-DDR2-800 5/5/5 : A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D D A4 RA4 D A5 RA5 D A6 RA6 D A7 RA7 D D D
Timing Patterns for 8bank devices x16
-DDR2-667 5/5/5 : A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D A4 RA4 D D A5 RA5 D D A6 RA6 D D A7 RA7 D D D
-DDR2-800 6/6/6 : A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D A4 RA4 D D A5 RA5 D D A6 RA6 D D A7 RA7 D D D D
-DDR2-800 5/5/5 : A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D A4 RA4 D D A5 RA5 D D A6 RA6 D D A7 RA7 D D D D
K4T1G084QE
K4T1G164QE
K4T1G044QE
bits 10 and 11.
tRRD(IDD)-x4/x8
tRRD(IDD)-x16
tRASmin(IDD)
LOW is defined as V
HIGH is defined as V
STABLE is defined as inputs stable at a HIGH or LOW level
FLOATING is defined as inputs at V
SWITCHING is defined as:
Parameter
tRCD(IDD)
tRFC(IDD)
tRC(IDD)
tCK(IDD)
tRP(IDD)
CL(IDD)
signals, and
inputs changing between HIGH and LOW every other data transfer (once per clock) for DQ signals not including
inputs changing between HIGH and LOW every other clock cycle (once per two clocks) for address and control
masks or strobes.
IN
IN
≤ V
≥ V
IL
IH
DDR2-800
(AC)
(AC)
127.5
5-5-5
12.5
57.5
12.5
7.5
2.5
10
45
5
max
min
REF
= V
DDQ
/2
DDR2-800
127.5
6-6-6
7.5
2.5
15
60
10
45
15
6
17 of 45
DDR2-667
127.5
5-5-5
7.5
15
60
10
45
15
5
3
Rev. 1.1 December 2008
Units
tCK
ns
ns
ns
ns
ns
ns
ns
ns
DDR2 SDRAM