k4s1g0732b Samsung Semiconductor, Inc., k4s1g0732b Datasheet - Page 8

• Manufacturer Part Number: k4s1g0732b
• Description: 32m X 8bit X 4 Banks Synchronous Dram
• Manufacturer: Samsung Semiconductor, Inc.

AC OPERATING TEST CONDITIONS
SDRAM stacked 1Gb B-die (x8)
Notes :
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
Row active to row active delay
RAS to CAS delay
Row precharge time
Row active time
Row cycle time
Last data in to row precharge
Last data in to Active delay
Last data in to new col. address delay
Last data in to burst stop
Col. address to col. address delay
Number of valid output data
AC input levels (Vih/Vil)
Input timing measurement reference level
Input rise and fall time
Output timing measurement reference level
Output load condition
Output
1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
(Fig. 1) DC output load circuit
and then rounding off to the next higher integer.
870Ω
Parameter
Parameter
3.3V
CAS latency=3
CAS latency=2
1200Ω
50pF
t
t
t
t
t
t
t
t
t
RAS
V
V
RRD
RCD
t
CCD
Symbol
t
RAS
RDL
CDL
DAL
BDL
RP
RC
OH
OL
(min)
(min)
(max)
(min)
(min)
(min)
(min)
(min)
(min)
(min)
(min)
(DC) = 0.4V, I
(V
(DC) = 2.4V, I
DD
= 3.3V ± 0.3V, T
OL
OH
= -2mA
= 2mA
A
= 0 to 70°C)
2 CLK + 20 ns
See Fig. 2
tr/tf = 1/1
Version
2.4/0.4
Value
1.4
1.4
100
-75
15
20
20
45
65
Output
2
2
1
1
1
1
(Fig. 2) AC output load circuit
Rev. 1.1 February 2004
Z0 = 50Ω
CMOS SDRAM
Unit
CLK
CLK
CLK
CLK
ea
ns
ns
ns
ns
us
ns
-
Vtt = 1.4V
Unit
50Ω
ns
50pF
V
V
V
Note
1
1
1
1
1
2
2
2
3
4