mt8vddt6464hg-40b Micron Semiconductor Products, mt8vddt6464hg-40b Datasheet - Page 19

• Manufacturer Part Number: mt8vddt6464hg-40b
• Description: 256mb, 512mb X64, Sr Pc3200 200-pin Ddr Sodimm
• Manufacturer: Micron Semiconductor Products

pdf: 09005aef80b577e4, source: 09005aef80921669
DDA8C32_64x64HG.fm - Rev. D 9/04 EN
39. During initialization, V
40. The current Micron part operates below the slow-
41. Random addressing changing and 50 percent of
42. Random addressing changing and 100 percent of
43. CKE must be active (high) during the entire time a
44. I
160
140
120
100
80
60
40
20
Figure 7: Pull-Down Characteristics
0
0.0
be equal to or less than V
V
even if V
42
supply and the input pin.
est JEDEC operating frequency of 83 MHz. As
such, future die may not reflect this option.
data changing at every transfer.
data changing at every transfer.
refresh command is executed. That is, from the
time the AUTO REFRESH command is registered,
CKE must be active at each rising clock edge, until
t
driven to a valid high or low logic level. I
REF later.
DD
TT
2N specifies the DQ, DQS, and DM to be
may be 1.35V maximum during power up,
of series resistance is used between the V
DD
0.5
/V
DD
Q are 0V, provided a minimum of
1.0
V
V
OUT
OUT
DD
(V)
(V)
DD
Q, V
1.5
+ 0.3V. Alternatively,
TT
, and V
2.0
Minimum
REF
DD
must
2
Q
TT
2.5
is
19
45. Whenever the operating frequency is altered, not
46. Leakage number reflects the worst case leakage
47. When an input signal is HIGH or LOW, it is
48. This is the DC voltage supplied at the DRAM and
256MB, 512MB (x64, SR) PC3200
-100
-120
-140
-160
-180
-200
-20
-40
-60
-80
0
0.0
similar to I
address and control inputs to remain stable.
Although I
I
including jitter, the DLL is required to be reset.
This is followed by 200 clock cycles (before READ
commands).
possible through the module pin, not what each
memory device contributes.
defined as a steady state logic HIGH or LOW.
is inclusive of all noise up to 20 MHz. Any noise
above 20 MHz at the DRAM generated from any
source other than that of the DRAM itself may not
exceed the DC voltage range of 2.6V ±0.1V.
Figure 8: Pull-Up Characteristics
DD
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2
F
is “worst case.”
0.5
DD
200-PIN DDR SODIMM
DD
2
F
2
, I
F
DD
1.0
except I
V
DD
2
Q - V
N
, and I
OUT
(V)
1.5
DD
DD
2
Q
©2004 Micron Technology, Inc.
2
Q
specifies the
are similar,
2.0
2.5