mt9v112 Micron Semiconductor Products, mt9v112 Datasheet - Page 40

• Manufacturer Part Number: mt9v112
• Description: 1/6-inch Soc Vga Cmos Digital Image Sensor
• Manufacturer: Micron Semiconductor Products

T able 12: Sensor Core Register Descriptions (continued)
09005aef8154a39d/09005aef8175e6cc
MT9V112_2.fm- Rev. A 1/05 EN
Bit 3
Column
Skip 2x —
Context B
Bit 2
Row Skip
2x—
Context B
Bit 1
Mirror
Columns
Bit 0
Mirror
Rows
R33:0—0x021 – Read Mode—Context A
Bit 10
Low-Power
Mode—
Context A
Bit 3
Column
Skip 2x —
Context A
Bit 2
Row Skip
2x—
Context A
R35:0—0x023 – Flash Control
Bit 15
Flash Strobe
Bit 14
Bit 13
Xenon Flash
Bits 12:11
Frame
Delay
Bit 10
End of
Reset
BIT FIELD
When READ mode context B is selected (bit 3, Reg0x0C8 = 1):
0: Normal readout.
1: READ out two columns, and then skip two columns (as with
rows).
When READ mode context B is selected (bit 3, Reg0x0C8 = 1):
0: Normal readout.
1: READ out two rows, then skip two rows (i.e., row 8, row 9,
row 12, row 13…).
Read out columns from right to left (mirrored). When set,
column readout starts from column (Col Start + Col Size) and
continues down to (Col Start + 1). When clear, readout starts at
Col Start and continues to (Col Start + Col Size - 1). This ensures
that the starting color is maintained.
Read out rows from bottom to top (upside down). When set,
row readout starts from row (Row Start + Row Size) and
continues down to (Row Start + 1). When clear, readout starts at
Row Start and continues to (Row Start + Row Size - 1). This
ensures that the starting color is maintained.
When READ mode, context A is selected (bit 3, Reg0x0C8 = 0):
0: Full power, maximum readout speed.
1: Low power. Maximum readout frequency is now half of the
master clock, and the pixel clock is automatically adjusted as
described for the pixel clock speed register.
When READ mode context A is selected (bit 3, Reg0x0C8 = 0):
0: Normal readout.
1: READ out two columns, and then skip two columns (as with
rows).
When READ mode context A is selected (bit 3, Reg0x0C8 = 0):
0: Normal readout.
1: READ out two rows, and then skip two rows (i.e., row 8, row
9, row 12, row 13…).
READ only bit that indicates whether FLASH_STROBE is enabled.
Reserved.
Enable Xenon flash. When set, the FLASH_STROBE output signal
is pulsed HIGH for the programmed period during vertical
blanking. This is achieved by keeping the integration time equal
to one frame and the pulse width less than the vertical blanking
time.
Delay of the flash pulse measured in frames.
0: In Xenon mode, the flash should be enabled after the
readout of a frame.
1: In Xenon mode, the flash should be triggered after the
resetting of a frame.
DESCRIPTION
40
SOC VGA DIGITAL IMAGE SENSOR
Micron Technology, Inc., reserves the right to change products or specificat ions wit hout not ice.
DEFAULT
(HEX)
0x0
0x0
0x0
0x0
0x1
0x0
0x0
0x0
0x0
0x0
0x1
—
SYNC’D TO
FRAME
START
©2004 Micron Technology, Inc. All rights reserved.
—
Y
Y
Y
Y
Y
Y
Y
Y
N
N
0
PRELIMINARY
MT9V112
FRAME
BAD
YM
YM
YM
YM
YM
YM
YM
—
N
N
N
0
WRITE
READ/
W
W
W
W
W
W
W
—
W
W
W
R