gs88136bgt-250v GSI Technology, gs88136bgt-250v Datasheet

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gs88136bgt-250v

Manufacturer Part Number
gs88136bgt-250v
Description
512k X 18, 256k X 32, 256k X 36 9mb Sync Burst Srams
Manufacturer
GSI Technology
Datasheet
100-pin TQFP & 165-bump BGA
Commercial Temp
Industrial Temp
Features
• IEEE 1149.1 JTAG-compatible Boundary Scan
• 1.8 V or 2.5 V +10%/–10% core power supply
• 1.8 V or 2.5 V I/O supply
• LBO pin for Linear or Interleaved Burst mode
• Internal input resistors on mode pins allow floating mode pins
• Byte Write (BW) and/or Global Write (GW) operation
• Internal self-timed write cycle
• Automatic power-down for portable applications
• JEDEC-standard 100-lead TQFP and 165-bump BGA
• RoHS-compliant 100-lead TQFP and 165-bump BGA
Functional Description
Applications
The GS88118/32/36B(T/D)-xxxV is a 9,437,184-bit high
performance synchronous SRAM with a 2-bit burst address
counter. Although of a type originally developed for Level 2
Cache applications supporting high performance CPUs, the
device now finds application in synchronous SRAM
applications, ranging from DSP main store to networking chip
set support.
Controls
Addresses, data I/Os, chip enable (E1, E2), address burst
control inputs (ADSP, ADSC, ADV) and write control inputs
(Bx, BW, GW) are synchronous and are controlled by a
positive-edge-triggered clock input (CK). Output enable (G)
and power down control (ZZ) are asynchronous inputs. Burst
cycles can be initiated with either ADSP or ADSC inputs. In
Burst mode, subsequent burst addresses are generated
internally and are controlled by ADV. The burst address
counter may be configured to count in either linear or
Rev: 1.02 6/2007
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
packages
packages available
Flow Through
Pipeline
3-1-1-1
2-1-1-1
512K x 18, 256K x 32, 256K x 36
Curr (x32/x36)
Curr (x32/x36)
9Mb Sync Burst SRAMs
Curr (x18)
Curr (x18)
tCycle
tCycle
t
t
KQ
KQ
Paramter Synopsis
1/36
interleave order with the Linear Burst Order (LBO) input. The
Burst function need not be used. New addresses can be loaded
on every cycle with no degradation of chip performance.
Flow Through/Pipeline Reads
The function of the Data Output register can be controlled by
the user via the FT mode pin (Pin 14). Holding the FT mode
pin low places the RAM in Flow Through mode, causing
output data to bypass the Data Output Register. Holding FT
high places the RAM in Pipeline mode, activating the rising-
edge-triggered Data Output Register.
SCD Pipelined Reads
The GS88118/32/36B(T/D)-xxxV is a SCD (Single Cycle
Deselect) pipelined synchronous SRAM. DCD (Dual Cycle
Deselect) versions are also available. SCD SRAMs pipeline
deselect commands one stage less than read commands. SCD
RAMs begin turning off their outputs immediately after the
deselect command has been captured in the input registers.
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable
(BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the Byte Write
control inputs.
Sleep Mode
Low power (Sleep mode) is attained through the assertion
(High) of the ZZ signal, or by stopping the clock (CK).
Memory data is retained during Sleep mode.
Core and Interface Voltages
The GS88118/32/36B(T/D)-xxxV operates on a 1.8 V or 2.5 V
power supply. All input are 1.8 V and 2.5 V compatible.
Separate output power (V
output noise from the internal circuits and are 1.8 V and 2.5 V
compatible.
-250
200
230
160
185
3.0
4.0
5.5
5.5
-200
170
195
140
160
3.0
5.0
6.5
6.5
-150
140
160
128
145
3.8
6.7
7.5
7.5
DDQ
GS88118/32/36B(T/D)-xxxV
) pins are used to decouple
Unit
mA
mA
mA
mA
ns
ns
ns
ns
© 2006, GSI Technology
250 MHz–150 MHz
1.8 V or 2.5 V V
1.8 V or 2.5 V I/O
DD

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gs88136bgt-250v Summary of contents

Page 1

... KQ 5.5 tCycle Curr (x18) 160 Curr (x32/x36) 185 1/36 GS88118/32/36B(T/D)-xxxV 250 MHz–150 MHz 2.5 V I/O ) pins are used to decouple DDQ -200 -150 Unit 3.0 3.8 ns 5.0 6.7 ns 170 140 mA 195 160 mA 6.5 7.5 ns 6.5 7.5 ns 140 128 mA 160 145 mA © 2006, GSI Technology DD ...

Page 2

... DDQ DQP DDQ DDQ DDQ © 2006, GSI Technology ...

Page 3

... DDQ DDQ DDQ © 2006, GSI Technology ...

Page 4

... DDQ DDQ DDQ DQP 51 A © 2006, GSI Technology ...

Page 5

... Scan Test Mode Select Scan Test Data In Scan Test Data Out Scan Test Clock Flow Through or Pipeline mode; active low Linear Burst Order mode; active low Core power supply I/O and Core Ground Output driver power supply 5/36 GS88118/32/36B(T/D)-xxxV © 2006, GSI Technology ...

Page 6

... DQA C DDQ V NC DQA D DDQ V NC DQA E DDQ V NC DQA F DDQ V NC DQA G DDQ DQA NC J DDQ V DQA NC K DDQ V DQA NC L DDQ V DQA NC M DDQ DDQ © 2006, GSI Technology ...

Page 7

... DDQ V DQB DQB D DDQ V DQB DQB E DDQ V DQB DQB F DDQ V DQB DQB G DDQ DQA DQA J DDQ V DQA DQA K DDQ V DQA DQA L DDQ V DQA DQA M DDQ DDQ © 2006, GSI Technology ...

Page 8

... DQPB C DDQ V DQB DQB D DDQ V DQB DQB E DDQ V DQB DQB F DDQ V DQB DQB G DDQ DQA DQA J DDQ V DQA DQA K DDQ V DQA DQA L DDQ V DQA DQA M DDQ V NC DQPA N DDQ © 2006, GSI Technology ...

Page 9

... Linear Burst Order mode; active low Scan Test Mode Select Scan Test Data In Scan Test Data Out Scan Test Clock Must Connect Low Core power supply I/O and Core Ground Output driver power supply 9/36 GS88118/32/36B(T/D)-xxxV I/Os; active low D © 2006, GSI Technology ...

Page 10

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS88118/32/36B(T/D)-xxxV Block Diagram Counter Load Register D Q Register D Q Register D Q Register D Q Register D Q Register D Q Register 10/36 GS88118/32/36B(T/D)-xxxV A Memory Array – DQx1 DQx9 © 2006, GSI Technology ...

Page 11

... Note: The burst counter wraps to initial state on the 5th clock. 11/36 GS88118/32/36B(T/D)-xxxV Function Linear Burst Interleaved Burst Flow Through Pipeline Active Standby A[1:0] A[1:0] A[1:0] A[1: BPR 1999.05.18 © 2006, GSI Technology ...

Page 12

... may be used in any combination with BW to write single or multiple bytes. D 12/36 GS88118/32/36B(T/D)-xxxV B B Notes and/ © 2006, GSI Technology ...

Page 13

... High High High High © 2006, GSI Technology ...

Page 14

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Simplified State Diagram X Deselect First Write Burst Write CR CW 14/36 GS88118/32/36B(T/D)-xxxV First Read Burst Read BW, and GW) control inputs, and © 2006, GSI Technology ...

Page 15

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Simplified State Diagram with G X Deselect First Write Burst Write 15/36 GS88118/32/36B(T/D)-xxxV First Read Burst Read CR © 2006, GSI Technology ...

Page 16

... DDn 16/36 GS88118/32/36B(T/D)-xxxV Value –0.5 to 4.6 –0 –0 +0.5 (≤ 4.6 V max.) DDQ –0 +0.5 (≤ 4.6 V max.) DD +/–20 +/–20 1.5 –55 to 125 –55 to 125 Typ. Max. Unit 1.8 2.0 V 2 © 2006, GSI Technology Unit Notes ...

Page 17

... Symbol Test conditions I/O OUT 17/36 GS88118/32/36B(T/D)-xxxV Typ. Max. Unit V + 0.3 V — DD 0.3*V V — DD Typ. Max. Unit ° ° 20% tKC DD IL Typ. Max. Unit © 2006, GSI Technology Notes 1 1 Notes 2 2 ...

Page 18

... Figure 1 Output Load 1 * 50Ω 30pF V DDQ/2 * Distributed Test Jig Capacitance Min – ≥ –100 –1 uA OUT DD Min = 1 – 0.4 V DDQ DDQ = 2.375 V 1.7 V — — © 2006, GSI Technology Max 1 uA 100 Max — — 0.4 V 0.4 V ...

Page 19

... GSI Technology Unit ...

Page 20

... GSI Technology ...

Page 21

... ADSC initiated read and E3 only sampled with ADSP and ADSC tS tOHZ tH Q(A) D(B) 21/36 GS88118/32/36B(T/D)-xxxV Read C+1 Read C+2 Read C+3 Cont Burst Read Burst Read Deselected with E1 E1 masks ADSP tKQ tLZ Q(C) Q(C+1) Q(C+2) Q(C+3) © 2006, GSI Technology Deselect tKQX tHZ ...

Page 22

... Flow Through Mode Timing Cont Write B Read C Read C+1 Read C+2 Read C+3 Read C tKL tKL tKC tKC Fixed High tS tH ADSC initiated read tKQ tOHZ tLZ D(B) Q(C) 22/36 GS88118/32/36B(T/D)-xxxV Cont Deselect Deselected with E1 tHZ Q(C+1) Q(C+2) Q(C+3) Q(C) © 2006, GSI Technology tKQX ...

Page 23

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Sleep Mode Timing Diagram tKH tKH tKC tKC tKL tKL tZZS tZZH 23/36 GS88118/32/36B(T/D)-xxxV 2. The duration of SB tZZR . The JTAG output DD . TDO should be left unconnected. SS © 2006, GSI Technology ...

Page 24

... Capture-DR state and then is placed between the TDI and TDO pins when the controller is moved to Shift-DR state. SAMPLE-Z, SAMPLE/PRELOAD and EXTEST instructions can be used to activate the Boundary Scan Register. Rev: 1.02 6/2007 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Description 24/36 GS88118/32/36B(T/D)-xxxV © 2006, GSI Technology ...

Page 25

... Control Signals Test Access Port (TAP) Controller Not Used 25/36 GS88118/32/36B(T/D)-xxxV · · · TDO GSI Technology JEDEC Vendor ID Code © 2006, GSI Technology 0 1 ...

Page 26

... JTAG Tap Controller State Diagram 1 1 Select Capture DR 0 Shift Exit1 DR 0 Pause Exit2 Update 26/36 GS88118/32/36B(T/D)-xxxV 1 Select Capture IR 0 Shift Exit1 IR 0 Pause Exit2 Update © 2006, GSI Technology ...

Page 27

... Z) and the Boundary Scan Register is connected between TDI and TDO when the TAP controller is moved to the Shift-DR state. RFU These instructions are Reserved for Future Use. In this device they replicate the BYPASS instruction. Rev: 1.02 6/2007 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. 27/36 GS88118/32/36B(T/D)-xxxV © 2006, GSI Technology ...

Page 28

... Instruction codes expressed in binary, MSB on left, LSB on right. 2. Default instruction automatically loaded at power-up and in test-logic-reset state. Rev: 1.02 6/2007 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Description 28/36 GS88118/32/36B(T/D)-xxxV Notes © 2006, GSI Technology ...

Page 29

... DD2 DD2 –300 1 uA 100 uA –1 – 1.7 V — 0.4 V — – 100 mV — V DDQ 100 mV V — JTAG Port AC Test Load DQ 50Ω 30pF V /2 DDQ * Distributed Test Jig Capacitance © 2006, GSI Technology ...

Page 30

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. tTKC tTKC tTKH tTKH tTH tTS tTH tTS tTKQ tTH tTS Min Max Unit — — — — ns — — ns 30/36 GS88118/32/36B(T/D)-xxxV tTKL tTKL © 2006, GSI Technology ...

Page 31

... All dimensions are in millimeters (mm). 2. Package width and length do not include mold protrusion. Rev: 1.02 6/2007 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. θ 0.10 0.15 1.40 1.45 0.30 0.40 — 0.20 e 22.0 22.1 20.0 20.1 16.0 16.1 b 14.0 14.1 0.65 — 0.60 0.75 1.00 — 0.10 — 7° 31/36 GS88118/32/36B(T/D)-xxxV E1 E © 2006, GSI Technology ...

Page 32

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. BOTTOM VIEW Ø0. Ø0. Ø0.40~0.60 (165x 1.0 10.0 13±0.05 B 0.20(4x) 32/36 GS88118/32/36B(T/D)-xxxV A1 CORNER 1.0 © 2006, GSI Technology ...

Page 33

... GS88118BGT-200V 512K x 18 GS88118BGT-150V 256K x 32 GS88136BGT-250V 256K x 32 GS88132BGT-200V 256K x 32 GS88132BGT-150V 256K x 36 GS88136BGT-250V 256K x 36 GS88136BGT-200V 256K x 36 GS88136BGT-150V 512K x 18 GS88118BGT-250IV 512K x 18 GS88118BGT-200IV Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS88118BT-150IVT. ...

Page 34

... GS88118BGT-150IV 256K x 32 GS88136BGT-250IV 256K x 32 GS88132BGT-200IV 256K x 32 GS88132BGT-150IV 256K x 36 GS88136BGT-250IV 256K x 36 GS88136BGT-200IV 256K x 36 GS88136BGT-150IV 512K x 18 GS88118BD-250V 512K x 18 GS88118BD-200V 512K x 18 GS88118BD-150V 256K x 32 GS88132BD-250V 256K x 32 GS88132BD-200V 256K x 32 GS88132BD-150V 256K x 36 ...

Page 35

... GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings. Rev: 1.02 6/2007 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. ...

Page 36

... DS/DateRev. Code: Old; Types of Changes New Format or Content 881xxB_V_r1 881xxB_V_r1; 881xxB_V_r1.02 Rev: 1.02 6/2007 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. • Creation of new datasheet • Updated Truth Tables Content 36/36 GS88118/32/36B(T/D)-xxxV Page;Revisions;Reason © 2006, GSI Technology ...

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