gs88136cgt-250v GSI Technology, gs88136cgt-250v Datasheet - Page 25

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gs88136cgt-250v

Manufacturer Part Number
gs88136cgt-250v
Description
512k X 18, 256k X 32, 256k X 36 9mb Sync Burst Srams
Manufacturer
GSI Technology
Datasheet
* For the value of M, see the BSDL file, which is available at by contacting us at apps@gsitechnology.com.
Identification (ID) Register
The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in
Capture-DR state with the IDCODE command loaded in the Instruction Register. The code is loaded from a 32-bit on-chip ROM.
It describes various attributes of the RAM as indicated below. The register is then placed between the TDI and TDO pins when the
controller is moved into Shift-DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins.
ID Register Contents
Rev: 1.00 9/2008
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Bit #
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
X
X
X
X
TDI
TMS
TCK
X
X
·
·
X
·
X
X
·
Not Used
X
Test Access Port (TAP) Controller
Bypass Register
Instruction Register
ID Code Register
2
31 30 29
0
JTAG TAP Block Diagram
Boundary Scan Register
X
·
1
0
Control Signals
X
25/36
·
·
X
· · ·
X
·
X
2
1
X
0
·
X
·
X
X
·
X
0
·
GS88118/32/36C(T/D)-xxxV
0 0 1 1 0 1 1 0 0 1
GSI Technology
TDO
JEDEC Vendor
ID Code
© 2008, GSI Technology
Preliminary
0
1

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