gs8662dt10bgd-450i GSI Technology, gs8662dt10bgd-450i Datasheet

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gs8662dt10bgd-450i

Manufacturer Part Number
gs8662dt10bgd-450i
Description
72mb Sigmaquad-ii+tm Burst Of 4 Sram
Manufacturer
GSI Technology
Datasheet
165-Bump BGA
Commercial Temp
Industrial Temp
Features
• 2.0 Clock Latency
• Simultaneous Read and Write SigmaQuad™ Interface
• JEDEC-standard pinout and package
• Dual Double Data Rate interface
• Byte Write controls sampled at data-in time
• Burst of 4 Read and Write
• Dual-Range On-Die Termination (ODT) on Data (D), Byte
• 1.8 V +100/–100 mV core power supply
• 1.5 V or 1.8 V HSTL Interface
• Pipelined read operation
• Fully coherent read and write pipelines
• ZQ pin for programmable output drive strength
• Data Valid Pin (QVLD) Support
• IEEE 1149.1 JTAG-compliant Boundary Scan
• 165-bump, 13 mm x 15 mm, 1 mm bump pitch BGA package
• RoHS-compliant 165-bump BGA package available
SigmaQuad™ Family Overview
The GS8662DT07/10/19/37BD are built in compliance with
the SigmaQuad-II+ SRAM pinout standard for Separate I/O
synchronous SRAMs. They are 75,497,472-bit (72Mb)
SRAMs. The GS8662DT07/10/19/37BD SigmaQuad SRAMs
are just one element in a family of low power, low voltage
HSTL I/O SRAMs designed to operate at the speeds needed to
implement economical high performance networking systems.
Rev: 1.00 5/2011
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Write (BW), and Clock (K, K) inputs
tKHKH
tKHQV
2.22 ns
0.45 ns
-450
72Mb SigmaQuad-II+
Burst of 4 SRAM
0.45 ns
2.5 ns
Parameter Synopsis
-400
1/29
Clocking and Addressing Schemes
The GS8662DT07/10/19/37BD SigmaQuad-II+ SRAMs are
synchronous devices. They employ two input register clock
inputs, K and K. K and K are independent single-ended clock
inputs, not differential inputs to a single differential clock input
buffer.
Because Separate I/O SigmaQuad-II+ B4 RAMs always
transfer data in four packets, A0 and A1 are internally set to 0
for the first read or write transfer, and automatically
incremented by 1 for the next transfers. Because the LSBs are
tied off internally, the address field of a SigmaQuad-II+ B4
RAM is always two address pins less than the advertised index
depth (e.g., the 4M x 18 has a 1M addressable index).
GS8662DT07/10/19/37BD-450/400/350/333/300
2.86 ns
0.45 ns
-350
1 mm Bump Pitch, 11 x 15 Bump Array
165-Bump, 13 mm x 15 mm BGA
TM
0.45 ns
3.0 ns
-333
Bottom View
0.45 ns
3.3 ns
-300
© 2011, GSI Technology
1.8 V and 1.5 V I/O
450 MHz–300 MHz
1.8 V V
DD

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gs8662dt10bgd-450i Summary of contents

Page 1

... SigmaQuad-II+ B4 RAM is always two address pins less than the advertised index depth (e.g., the has a 1M addressable index). Parameter Synopsis -400 -350 2.5 ns 2.86 ns 0.45 ns 0.45 ns 1/29 450 MHz–300 MHz 1 1.8 V and 1.5 V I/O Bottom View -333 -300 3.0 ns 3.3 ns 0.45 ns 0.45 ns © 2011, GSI Technology DD ...

Page 2

... DDQ DDQ DDQ DDQ DDQ REF DDQ DDQ DDQ TMS © 2011, GSI Technology TDI ...

Page 3

... DDQ DDQ DDQ DDQ DDQ REF DDQ DDQ DDQ TMS © 2011, GSI Technology TDI ...

Page 4

... DDQ DDQ DDQ DDQ REF DDQ DDQ DDQ TMS © 2011, GSI Technology TDI ...

Page 5

... D14 Q14 DD DDQ V Q13 D13 DD DDQ DDQ DDQ REF V D12 Q4 DD DDQ V Q12 D3 DD DDQ V D11 Q11 SS DDQ V D10 Q10 TMS © 2011, GSI Technology TDI ...

Page 6

... Output — Input — Input — Output — Input — Input Active Low Output — Output — Supply 1.8 V Nominal Supply 1 1.5 V Nominal Supply — Output — Low = Low Impedance Range Input High/Float = High Impedance Range — — © 2011, GSI Technology ...

Page 7

... Beat 4 1 Rev: 1.00 5/2011 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8662DT07/10/19/37BD-450/400/350/333/300 BW1 D0–D8 1 Data In 0 Don’t Care 0 Data In 0 Don’t Care 7/29 D9–D17 Don’t Care Data In Data In Data In © 2011, GSI Technology ...

Page 8

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8662DT07/10/19/37BD-450/400/350/333/300 Byte 2 Byte 1 D9–D17 D0–D8 Written Written Beat 2 Beat 3 /2 (i.e., to the switch point of the diff-amp receiver), which could cause DDQ 8/29 Byte 2 Byte 1 Byte 2 D9–D17 D0–D8 D9–D17 Written Unchanged Written Beat 4 © 2011, GSI Technology ...

Page 9

... Don’t Care Data In Don’t Care Don’t Care Data In Don’t Care Data In Don’t Care Data In Don’t Care Data In Data In Data In Data In Data In Data In Data In Data In Data In © 2011, GSI Technology Q K ↑ n+3½ — — — — Q3 — Q3 ...

Page 10

... Don’t Care Data In Don’t Care Data In D0–D3 Don’t Care Data In Don’t Care Data In 10/29 D9–D17 Don’t Care Don’t Care Data In Data In D4–D7 Don’t Care Don’t Care Data In Data In © 2011, GSI Technology ...

Page 11

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8662DT07/10/19/37BD-450/400/350/333/300 State Diagram Power-Up READ WRITE WRITE Write Address WRITE D Count = 2 D Count = D Count + 1 Always Write Address 11/29 Write NOP Load New WRITE D Count = 2 D Count = 0 Always DDR Write WRITE D Count = 1 Increment © 2011, GSI Technology ...

Page 12

... DDQ +/–100 +/–100 125 –55 to 125 Typ. Max. 1.8 1.9 V — 0.05 — DDQ , followed by signal inputs. The power DD DDQ REF Typ. Max 100 © 2011, GSI Technology Unit Unit Unit °C °C ...

Page 13

... JB (C°/W) Airflow = 2 m/s 17.349 9.292 Max Units 0.05 V DDQ V + 0.3 V DDQ V – 0.1 V REF V + 0.3 V DDQ 0 DDQ Max Units 0.08 V DDQ + 0 0.5 V DDQ V – 0.2 V REF – 0 0.5 V DDQ 0.2 V © 2011, GSI Technology θ JC (C°/W) 2.310 Notes — 2,3 2,3 Notes — 1,2,3 1,2,3 4,5 4,5 ...

Page 14

... V ILDOFF ODT IN DD Output Disable OUT DDQ 14/29 Typ. Max. Unit Conditions 1.25 0. V/ns 0. DDQ Min. Max – – – – © 2011, GSI Technology ...

Page 15

... GSI Technology Notes Notes ...

Page 16

... DD © 2011, GSI Technology ...

Page 17

... Rev: 1.00 5/2011 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8662DT07/10/19/37BD-450/400/350/333/300 17/29 © 2011, GSI Technology ...

Page 18

... Rev: 1.00 5/2011 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8662DT07/10/19/37BD-450/400/350/333/300 18/29 © 2011, GSI Technology ...

Page 19

... Rev: 1.00 5/2011 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8662DT07/10/19/37BD-450/400/350/333/300 19/29 © 2011, GSI Technology ...

Page 20

... Boundary Scan Register is described in the Scan Order Table following. The Boundary Scan Rev: 1.00 5/2011 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8662DT07/10/19/37BD-450/400/350/333/300 TDO should be left unconnected Description 20/29 . The JTAG output DD © 2011, GSI Technology ...

Page 21

... ID Code Register · · · · Control Signals Test Access Port (TAP) Controller See BSDL Model 21/29 · · TDO GSI Technology JEDEC Vendor ID Code © 2011, GSI Technology 0 1 ...

Page 22

... JTAG Tap Controller State Diagram 1 1 Select Capture DR 0 Shift Exit1 DR 0 Pause Exit2 Update 22/29 1 Select Capture IR 0 Shift Exit1 IR 0 Pause Exit2 Update © 2011, GSI Technology ...

Page 23

... Forces all RAM output drivers to High-Z. GSI private instruction. Captures I/O ring contents. Places the Boundary Scan Register between TDI and TDO. GSI private instruction. GSI private instruction. Places Bypass Register between TDI and TDO. 23/29 Notes © 2011, GSI Technology ...

Page 24

... V – –300 1 uA 100 uA –1 – – 0.2 V — DD — 0 – 0.1 V — DD — 0.1 V JTAG Port AC Test Load TDO 50Ω 30pF Distributed Test Jig Capacitance © 2011, GSI Technology Notes ...

Page 25

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8662DT07/10/19/37BD-450/400/350/333/300 JTAG Port Timing Diagram tTKH tTKH tTKL tTKL tTH tTS tTH tTS tTKQ tTH tTS Min Max Unit 50 — ns — — — — — ns 25/29 © 2011, GSI Technology ...

Page 26

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8662DT07/10/19/37BD-450/400/350/333/300 BOTTOM VIEW A1 CORNER Ø0. Ø0. Ø0.40~0.60 (165x 1.0 10.0 13±0.05 B 0.20(4x) 26/ 1.0 © 2011, GSI Technology ...

Page 27

... GS8662DT10BD-333I GS8662DT10BD-300I GS8662DT10BGD-450 GS8662DT10BGD-400 Notes: 1. For Tape and Reel add the character “T” to the end of the part number. Example: GS8662DTxxD-300T Commercial Temperature Range Industrial Temperature Range. Rev: 1.00 5/2011 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. ...

Page 28

... Ordering Information—GSI SigmaQuad-II+ SRAM (Continued) 1 Org Part Number GS8662DT10BGD-350 GS8662DT10BGD-333 GS8662DT10BGD-300 GS8662DT10BGD-450I GS8662DT10BGD-400I GS8662DT10BGD-350I GS8662DT10BGD-333I GS8662DT10BGD-300I GS8662DT19BD-450 GS8662DT19BD-400 GS8662DT19BD-350 GS8662DT19BD-333 GS8662DT19BD-300 GS8662DT19BD-450I GS8662DT19BD-400I GS8662DT19BD-350I ...

Page 29

... Format/Content Creation of datasheet 29/29 Speed Package T J (MHz) 165-bump BGA 300 C 165-bump BGA 450 I 165-bump BGA 400 I 165-bump BGA 350 I 165-bump BGA 333 I 165-bump BGA 300 I 450 C 400 C 350 C 333 C 300 C 450 I 400 I 350 I 333 I 300 I Description of changes © 2011, GSI Technology 2 ...

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