gs82032agt-6i GSI Technology, gs82032agt-6i Datasheet

gs82032agt-6i

Manufacturer Part Number

gs82032agt-6i

Description

2mb Synchronous Burst Sram

Manufacturer

GSI Technology

Datasheet

1.GS82032AGT-6I.pdf (22 pages)

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TQFP

Commercial Temp

Industrial Temp

Features

• FT pin for user-configurable flow through or pipelined opera-

• Single Cycle Deselect (SCD) operation

• 3.3 V +10%/–5% core power supply

• 2.5 V or 3.3 V I/O supply

• LBO pin for Linear or Interleaved Burst mode

• Internal input resistors on mode pins allow floating mode pins

• Default to Interleaved Pipelined mode

• Byte Write (BW) and/or Global Write (GW) operation

• Common data inputs and data outputs

• Clock Control, registered, address, data, and control

• Internal self-timed write cycle

• Automatic power-down for portable applications

• JEDEC standard 100-lead TQFP package

• RoHS-compliant 100-lead TQFP package available

Functional Description

Applications

The GS82032A is a 2,097,152-bit high performance

synchronous SRAM with a 2-bit burst address counter.

Although of a type originally developed for Level 2 Cache

applications supporting high performance CPUs, the device

now finds application in synchronous SRAM applications,

ranging from DSP main store to networking chip set support.

Controls

Addresses, data I/Os, chip enables (E

control inputs (ADSP, ADSC, ADV), and write control inputs

(Bx, BW, GW) are synchronous and are controlled by a

positive-edge-triggered clock input (CK). Output enable (G)

and power down control (ZZ) are asynchronous inputs. Burst

cycles can be initiated with either ADSP or ADSC inputs. In

Burst mode, subsequent burst addresses are generated

internally and are controlled by ADV. The burst address

Rev: 1.13 1/2009

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

tion

Through

Pipeline

3-1-1-1

2-1-1-1

Flow

tCycle

2Mb Synchronous Burst SRAM

, E

155 mA

100 mA

5.5 ns

3.2 ns

9.1 ns

), address burst

-180

8 ns

Parameter Synopsis

140 mA

90 mA

3.5 ns

8.5 ns

10 ns

-166

1/22

6 ns

64K x 32

130 mA

10.5 ns

85 mA

6.6 ns

3.8 ns

counter may be configured to count in either linear or

interleave order with the Linear Burst Order (LBO) input. The

Burst function need not be used. New addresses can be loaded

on every cycle with no degradation of chip performance.

Flow Through/Pipeline Reads

The function of the Data Output Register can be controlled by

the user via the FT mode pin (Pin 14 in the TQFP). Holding

the FT mode pin low places the RAM in Flow Through mode,

causing output data to bypass the Data Output Register.

Holding FT high places the RAM in Pipelined mode,

activating the rising-edge-triggered Data Output Register.

SCD Pipelined Reads

The GS82032A is an SCD (Single Cycle Deselect) pipelined

synchronous SRAM. DCD (Dual Cycle Deselect) versions are

also available. SCD SRAMs pipeline deselect commands one

stage less than read commands. SCD RAMs begin turning off

their outputs immediately after the deselect command has been

captured in the input registers.

Byte Write and Global Write

Byte write operation is performed by using Byte Write enable

(BW) input combined with one or more individual byte write

signals (Bx). In addition, Global Write (GW) is available for

writing all bytes at one time, regardless of the Byte Write

control inputs.

Sleep Mode

Low power (Sleep mode) is attained through the assertion

(High) of the ZZ signal, or by stopping the clock (CK).

Memory data is retained during Sleep mode.

Core and Interface Voltages

The GS82032A operates on a 3.3 V power supply and all

inputs/outputs are 3.3 V- and 2.5 V-compatible. Separate

output power (V

from the internal circuit.

-150

9 ns

GS82032AT-180/166/150/133/100/66/4/5/6

-133 (-4)

115 mA

80 mA

7.5 ns

12 ns

10 ns

4 ns

DDQ

-100 (-5)

) pins are used to decouple output noise

90 mA

65 mA

10 ns

15 ns

12 ns

5 ns

-66 (-6)

12.5 ns

65 mA

50 mA

20 ns

18 ns

6 ns

3.3 V and 2.5 V I/O

180 MHz–66 MHz

3.3 V V

Related parts for gs82032agt-6i

gs82032agt-6i Summary of contents

... Burst address counter advance enable; active low Address Strobe (Processor, Cache Controller); active low Sleep Mode control; active high Flow Through or Pipeline mode; active low Linear Burst Order mode; active low Core power supply I/O and Core Ground Output driver power supply 3/22 © 2000, GSI Technology ...

Page 4

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS82032AT-180/166/150/133/100/66/4/5/6 GS82032A Block Diagram Counter Load Register D Q Register D Q Register D Q Register D Q Register D Q Register D Q Register 4/22 A Memory Array – DQx1 DQx8 © 2000, GSI Technology ...

Page 5

... Note: The burst counter wraps to initial state on the 5th clock. 5/22 Function Linear Burst Interleaved Burst Flow Through Pipeline Active Standby A[1:0] A[1:0] A[1:0] A[1: © 2000, GSI Technology ...

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... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS82032AT-180/166/150/133/100/66/4/5/6 Simplified State Diagram X Deselect First Write Burst Write 8/ First Read Burst Read and Write ( BW, and GW) control © 2000, GSI Technology ...

Page 9

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS82032AT-180/166/150/133/100/66/4/5/6 Simplified State Diagram with G X Deselect First Write Burst Write 9/ First Read Burst Read CR © 2000, GSI Technology ...

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... GSI Technology -66 Unit Min Max 12.5 — ns — 1.5 — ns 1.5 — — ns — — — ns 1.3 — ns 1.5 — — ...

Page 15

... ADSC initiated read and E3 only sampled with ADSP and ADSC tS tOHZ tH Q(A) D(B) 15/22 Read C+1 Read C+2 Read C+3 Cont Burst Read Burst Read Deselected with E1 E1 masks ADSP tKQ tLZ Q(C) Q(C+1) Q(C+2) Q(C+3) © 2000, GSI Technology Deselect tKQX tHZ ...

Page 16

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS82032AT-180/166/150/133/100/66/4/5/6 Flow Through Mode Timing Cont Write B Read C Read C+1 Read C+2 Read C+3 Read C tKL tKL tKC tKC Fixed High tS tH ADSC initiated read tKQ tOHZ tLZ D(B) Q(C) 16/22 Cont Deselect Deselected with E1 tHZ Q(C+1) Q(C+2) Q(C+3) Q(C) © 2000, GSI Technology tKQX ...

Page 17

... Rev: 1.13 1/2009 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS82032AT-180/166/150/133/100/66/4/5/6 Sleep Mode Timing tKH tKH tKC tKC tKL tKL tZZS tZZH 17/22 tZZR © 2000, GSI Technology ...

Page 18

... Rev: 1.13 1/2009 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS82032AT-180/166/150/133/100/66/4/5/6 GS82032A Output Driver Characteristics 1 1 Out (Pull Dow Out (Pull Up) DDQ 18/22 V DDQ I Out VOut V SS 2.5 3 3 © 2000, GSI Technology ...

Page 19

... All dimensions are in millimeters (mm). 2. Package width and length do not include mold protrusion. Rev: 1.13 1/2009 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS82032AT-180/166/150/133/100/66/4/5/6  0.10 0.15 1.40 1.45 0.30 0.40 — 0.20 e 22.0 22.1 20.0 20.1 16.0 16.1 b 14.0 14.1 0.65 — 0.60 0.75 1.00 — 0.10 7 — 19/ © 2000, GSI Technology ...

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... GS82032AGT-100 64K x 32 GS82032AGT-66 64K x 32 GS82032AGT-4 64K x 32 GS82032AGT-5 64K x 32 GS82032AGT-6 64K x 32 GS82032AGT-180I 64K x 32 GS82032AGT-166I 64K x 32 GS82032AGT-150I Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS82032AT-150IT. ...

Page 21

... GS82032AGT-4I 64K x 32 GS82032AGT-5I 64K x 32 GS82032AGT-6I Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS82032AT-150IT. 2. The speed column indicates the cycle frequency (MHz) of the device in Pipelined mode and the latency (ns) in Flow Through mode. ...

Page 22

... Removed all references to 200 MHz parts (no longer active) Content • Complete rewrite of datasheet in order to reflect parts Content available • Reactiviated 180 MHz speed bin Content • Updated format • Added Pb-free information for TQFP Content • Updated Pb-free to RoHS-compliant Content 22/22 © 2000, GSI Technology ...

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