gs820e32a GSI Technology, gs820e32a Datasheet - Page 3
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gs820e32a
Manufacturer Part Number
gs820e32a
Description
2mb Synchronous Burst Sram
Manufacturer
GSI Technology
Datasheet
1.GS820E32A.pdf
(20 pages)
TQFP Pin Description
Rev: 1.08 1/2009
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
ADSP, ADSC
Symbol
B
B
A
E
V
DQ
DQ
DQ
DQ
ADV
LBO
V
GW
V
BW
C
NC
A
CK
0
1
ZZ
E
FT
DDQ
G
A
, A
, B
, B
, E
DD
SS
2
C
D
A
B
1
B
D
3
Type
I/O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
3/20
Address Strobe (Processor, Cache Controller); active low
Address field LSBs and Address Counter preset Inputs
Byte Write Enable for DQ
Byte Write Enable for DQ
Burst address counter advance enable; active low
Global Write Enable—Writes all bytes; active low
Byte Write—Writes all enabled bytes; active low
Flow Through or Pipeline mode; active low
Linear Burst Order mode; active low
Sleep Mode control; active high
Clock Input Signal; active high
Data Input and Output pins
Output driver power supply
Output Enable; active low
Chip Enable; active high
Chip Enable; active low
I/O and Core Ground
Core power supply
Description
Address Inputs
No Connect
A
C
, DQ
, DQ
B
D
Data I/Os; active low
Data I/Os; active low
GS820E32AT-180/166/133/4/5
© 2000, GSI Technology