saa5288 NXP Semiconductors, saa5288 Datasheet - Page 28

• Manufacturer Part Number: saa5288
• Description: Microcontroller With Full Screen Screen Display
• Manufacturer: NXP Semiconductors

Philips Semiconductors
7.13
The vertical display timing also resynchronizes to every
sync pulse received. This means that the device can
produce a stable display on both 625 and 525-line
screens. Display starts on the 41st line of each field and
continues for 250 lines, or until the end of the field.
Normally, television displays are interlaced, i.e. only every
other TV line is displayed on each field. It is normal to
de-interlace teletext displays to prevent the displayed
characters flickering up and down. In many TV designs this
is achieved by modulating the vertical deflection current
slightly in such a way that odd fields are shifted up and
even fields are shifted down on the screen so that
lines 1 and 314, 2 and 315 etc. are overlaid. The FRAME
output is provided to facilitate this.
If the active edge of Vsync occurs in the first half of a TV
line this is an even field and the FRAME output should be a
logic 0 for this field. Similarly, if VSync is in the second half
of the line this is an odd field and FRAME should be a
logic 1. The algorithm used to derive FRAME is such that
a consistent output will be obtained no matter where the
VSync signal is relative to the HSync signal, even if VSync
occurs at the start and mid-points of a line.
Setting the TXT0.DISABLE FRAME bit forces the FRAME
output to a logic 0. Setting the TXT0.AUTO FRAME bit
causes the FRAME output to be active when just text is
being displayed but to be forced to 0 when any video is
being displayed. This allows the de-interlacing function to
take place with virtually no software intervention.
Some TV architectures do not use the FRAME output but
accomplish the de-interlacing function in the vertical
deflection IC, under software control, by delaying the start
of the scan for one field by half a line, so that lines in this
field are moved up by one TV line. In such TVs, VSync
may occur in the first half of the line at the start of an odd
field and in the second half of the line at the start of an even
field. In order to obtain correct de-interlacing in these
circumstances, theTXT1.FIELD POLARITY must be set to
reverse the assumptions made by the vertical timing
circuits on the timing of VSync in each field. The start of the
display may be delayed by a line. The ‘Field Polarity’ bit
does not affect the FRAME output.
1997 Jun 24
TV microcontroller with full screen
On Screen Display (OSD)
Vertical timing
28
7.14
The position of the display relative to the HSync and
VSync inputs can be varied over a limited range to allow
for optimum TV set-up.
The horizontal position is controlled by the X0 and X1 bits
in SFR TXT16. Table 16 gives the time from the active
edge of the HSync signal to the start of the display area for
each setting of X0 and X1.
Table 16 Display horizontal position
The line on which the display area starts depends on
whether the display is 625-line or 525-line and on the
setting of the Y0 to Y2 bits in SFR TXT16. Table 17 gives
the first display line for each setting of Y0 to Y2, for both
625 and 525-line display.
On the other field, the display starts on the equivalent line.
Table 17 Display vertical position
Y2
0
0
0
0
1
1
1
1
X1
0
0
1
1
Display position
Y1
0
0
1
1
0
0
1
1
X0
0
1
0
1
Y0
0
1
0
1
0
1
0
1
FIRST LINE FOR DISPLAY
625-LINE
42
44
46
48
34
36
38
40
HSYNC DISPLAY
Preliminary specification
17.2
16.2
15.2
14.2
( s)
SAA5288
525-LINE
28
30
32
34
20
22
24
26