w83c554f Winbond Electronics Corp America, w83c554f Datasheet - Page 132

• Manufacturer Part Number: w83c554f
• Description: System I/o Controller With Pci Arbiter & Ultradma/33 Ide Controller
• Manufacturer: Winbond Electronics Corp America

W83C554F
4.4.2
Primary/Secondary Status Registers (default = 00h)
Function:
Type:
Bit Description:
WINBOND ELECTRONICS CORP. AMERICA
Bit 7:
Bit 6:
Bit 5:
Bit [4:3]:
Bit 2:
Bit 1:
Bit 0:
Read/Write
Primary/Secondary Status Registers
These register descriptions are the same and are used to control the two IDE ports under the protocol,
which requires a multi-word DMA-capable disk drive in order for the W83C554F to function as a PCI
master.
MT. The multithread bit is hardwired to a 0b to indicate that both channels operate
independently and can be used at the same time.
SDC. Slave drive DMA capable is a status bit that is set by a driver/program to indicate that the
slave drive on the indicated port is DMA capable and that the W83C554F is initialized for
optimal performance. This bit is a 0b after a reset.
MDC. Master drive DMA capable is a status bit that is set by a driver/application to indicate that
the master drive on the indicated port is DMA capable and that the W83C554Fis initialized for
optimal performance. This bit is a 0b after a reset.
These bits are hardwired to a 0b.
IRQ. This bit is set by the rising edge of the associated ports IDE_IRQ signal. This bit is
cleared by writing a 1b to it. On data transfers from an IDE device to system memory, this bit
will be delayed until all data has been transferred to memory. This bit is a 0b after a reset. A
noise filter has been added to the IDE_IRQ inputs.
ERR. This bit is set when the controller encounters an error when transferring data to/from
system memory. The specific error conditions are errors that would cause bit 8, 12, or 13 of the
Device Status register to become set. This bit is reset by writing a 1b to it. This bit is a 0b after
a reset.
ACT. This bit is set when the BMEN bit of the command register is written with a 1b. It is
cleared when the BMEN bit is written with a 0b (abort condition) or when the last transfer for a
region is performed where EOT is set in that region descriptor (normal termination).
Register Information
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