w83c554f Winbond Electronics Corp America, w83c554f Datasheet - Page 51

• Manufacturer Part Number: w83c554f
• Description: System I/o Controller With Pci Arbiter & Ultradma/33 Ide Controller
• Manufacturer: Winbond Electronics Corp America

W83C554F
One 82C54 counter/timer, with three channels, is included in the W83C554F. The clocks for the three channels are
connected to the 14.31818 MHz clock through a divide-by-twelve counter. The gate inputs of counters 0 and 1 are tied high
so that they are always enabled. The gate input of counter 2 is tied to bit 0 of Port B, inside the chip. The output of counter 0
is connected to the IRQ0 input of the interrupt controllers. The output of counter 1 goes to the arbitration logic for a refresh
request. Finally, the output of counter 2 goes to an AND gate, which drives the SPKR output pin. The other input to this
AND gate comes from bit 1 of Port B.
The W83C554F contains a programmable pin, eight master PCI arbiter which can be tailored to meet system-specific
arbitration requirements. Pin 16 is available to strap the arbiter into its disabled state on power-up. A weak 2.2K ohm pull-
down resistor is recommended for this in systems using an external arbiter. When disabled, the "Function 0" ISA bridge uses
the REQ#/GNT# pair on pins 25 and 26, and the "Function 1" IDE controller uses the REQ#/GNT# pair on pins 27 and 28.
If no pull-down resistor is used on pin 16, the on-chip arbiter will be enabled after power up.
When in the active state, the eight masters supported by the W83C554F are its two internal masters (ISA bridge and IDE
controller), the system CPU, and REQ#/GNT#[4:0] which are available to the system designer. The PCI5TH# function of
pin 13 can be used to change the fifth REQ#/GNT# pair (on pins 6 and 7) to FLSHREQ#/FLSHACK# if desired (in either
CPU mode). This PCI5TH# function is over rider by the ARBDIS# pin when enabled, meaning pins 6 and 7 will always be
FLSHREQ# and FLSHACK# regardless of the strap option at PCI5TH# (pin 13).
FLSHREQ#/FLSHACK# are only used in Guaranteed Access Timing (GAT) mode. In GAT mode, before Function 0 makes
a request for the PCI bus, it asserts FLSHREQ# to the system and waits for FLSHACK# to be asserted. The system can use
this signal to flush all PCI buffers so that the W83C554F can be granted unimpeded access to main memory. When Function
0 (PCI-to-ISA bridge) is not in GAT mode, it behaves as any other PCI master device.
Upon power-up, the arbiter defaults to a "round-robin" rotation scheme allowing all PCI masters equal access to the local bus.
If desired, the relative priority of each REQ/GNT pair can be custom tailored to a specific system design via the PCI Priority
Control Register 1 at Index 80h in the Function 0 PCI Configuration Space. Note that all masters are assured of access to the
PCI bus at least once during each rotation regardless of the programming options chosen. (This is required for PCI
compliance, so no functions are "locked out" for an extended period).
WINBOND ELECTRONICS CORP. AMERICA
3.21
3.22
82C54 Counter/Timer
PCI Arbiter
System Architecture
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