n82802 Intel Corporation, n82802 Datasheet - Page 43

• Manufacturer Part Number: n82802
• Description: Firmware Hub Fwh
• Manufacturer: Intel Corporation

5.4.1.4.
5.4.1.5.
Datasheet
Figure 11.
Note:
R
Write Waveforms
Response To Invalid Fields
During FWH operations, the Intel FWH will not explicitly indicate that it has received invalid field
sequences. The response to specific invalid fields or sequences is as follows:
Once valid START, IDSEL, and IMSIZE fields are received, the Intel FWH always will respond to
subsequent inputs as if they were valid. As long as the states of FWH [3:0] and FWH4 are known, the
response of the Intel FWH to signals received during the FWH cycle should be predictable. The Intel
FWH will make no attempt to check the validity of incoming flash operation commands.
1.
FWH[3:0]
• Address out of range: The Intel FWH address sequence is 7 fields long (28 bits), but only the last
• Invalid IMSIZE field: If the Intel FWH receives an invalid size field during a read or write
• Non-page-aligned address: The Intel FWH assumes that multibyte read addresses are page aligned
Clock
Cycle
Write Waveforms
16
17
FWH4
five address fields (20 bits) will be decoded by an 8-Mbit FWH. (For a 4-Mbit density, the most-
significant bit (FWH3) in the third address field also will be ignored.) The Intel FWH will respond
to these lower addresses, regardless of the value of the more-significant address bits. Address A22
has the special function of directing reads and writes to the flash core (A22 = 1) or to the register
space (A22 = 0).
operation, the internal state machine will reset and no operation will be attempted. The Intel FWH
will generate no response of any kind in this situation. Invalid-size fields for a read cycle are
anything but 0000. Invalid-size fields for a write cycle are anything but 0000. When accessing
register space, invalid field sizes are anything but 0000.
(i.e., for a 32-byte access, the lower 5 address bits will be zero). If they are not zero, the first byte
of data returned by the Intel FWH will correspond to that explicit address, and subsequent data will
be as if the first address was indeed page aligned.
CLK
Field contents are valid on the rising edge of the present clock cycle.
Name
TAR0
TAR1
Field
STR
IDS
Field Contents
1111 (float)
FWH[3:0]
1111
IMADDR
1
FWH[3:0]
Direction
Float then
then float
OUT
IN
IMS
DATA
In this clock cycle, the FWH has driven the bus to all
1s and then floats the bus prior to the next clock
cycle. This is the first part of the bus “turnaround
cycle.”
The master (Intel ICH) resumes control of the bus
during this cycle.
TAR
SYN
C
Intel
TAR
®
Comments
82802AB/AC Firmware Hub
43