hi-6010 Holt Integrated Circuits, Inc., hi-6010 Datasheet - Page 4

• Manufacturer Part Number: hi-6010
• Description: Transmitter / Receiver For 8-bit Bus
• Manufacturer: Holt Integrated Circuits, Inc.

The transmitter logic is independent of the receiver except in
the following ways:
In self test the transmitter outputs route to the receiver inputs
internally and the TXD0 and TXD1 outputs are inhibited.
When parity is enabled, both the receiver and transmitter are
affected. Odd parity is automatically generated in the 32nd
bit if this option is selected.
HARDWARE CONTROL OF THE TRANSMITTER
PIN 2 - WEF
This output goes high for 1 transmitter error and 3 receiver
errors. To determine which error is being flagged, read the
Status Register. Reading the Status Register also clears the
error flag. The transmitter will not function until the error is
cleared. It can also be cleared by MR going high.
The only possible transmitter error is generated when running
in 8 bit mode. For the transmitter this means loading the last 3
bytes while the transmission is in progress. Failure to load a
byte before the previous byte's 8th bit is transmitted will
generate the error, indicated by status bit SR7 set to a 1.
PIN 3 -
This pin is a hardware gate for transmissions.
transmitter buffer is loaded and Control Register bit CR0 is a
one, the only inhibit of the transmitter would be for
one. When taken low, transmission of an ARINC word is
enabled. It may be pulsed to release each transmitted word.
PIN 4 - TXC
The data rate of transmission is controlled by this pin. This
clock must be 4X the desired date rate.
PIN 5 - HFS and the CONTROL REGISTER
This pin along with the Control Register sets the functioning of
the chip. For the transmitter:
PIN 6 - MR
The chip is initialized whenever this pin goes high. The
Control Register is set to 0X10 0101 (CR7 - CR0). For the
transmitter this sets up 8 bit mode with the transmitter
enabled.
USING THE TRANSMITTER
CONTROL
BIT NAME
CR0
CR4
CR5
CTS
PROGRAM
VALUE
0
1
0
1
0
1
0
1
VALUE
PIN 5
X
X
X
X
0
0
1
1
1.
2.
Self Test
Parity Option
Transmitter is disabled
Transmitter is enabled
Not in self test
Self test enabled
8 bit mode + data in 32nd bit
8 bit mode + parity enabled
32 bit mode with parity enabled
8 bit mode with parity enabled
OPERATION
HOLT INTEGRATED CIRCUITS
CTS
to be a
If the
HI-6010
4
PIN 7 - TXE
Whenever a transmission begins, this pin goes low and
returns high after the transmission is complete.
PIN 9 - TXRDY
Whenever TXRDY is a one, data may be written into the
transmitter buffer. In 8 bit "one byte at a time" mode, this pin
may be monitored to indicate when to write the next 8 bits.
PIN 10 - TXD0 and PIN 11 - TXD1
TXD0 will go high during a transmission if the data is zero.
TXD1 goes high if data is a one. When both pins are low this
is referred to as the Null state.
transmitter chip, such as the HI-3182, HI-3183, HI-8585 or
HI-8586 is connected to these pins to translate the 5 volt
levels to the proper ARINC bus levels.
Data is not output when the HI-6010 is in self-test mode.
SOFTWARE CONTROL OF THE TRANSMITTER
By writing into the Control Register and reading the Status
Register, the controlling processor can operate the
transmitter independent of the flags at the pins.
Transmission can be initiated by changing CR0 from a 0 to a 1
after the transmitter buffer has been loaded. Then the Status
Register may be monitored as follows:
APPLICATIONS TIPS
Cabling Noise
The HI-6010 has TTL compatible inputs and therefore
they are susceptible to noise near ground. If the data bus
is passed by ribbon cable or the equivalent to the device
under test, it is possible to get significant glitches on the
Master Reset line. The problem will appear to be a pattern
sensitive failure. One cure is simply to adequately bypass
Master Reset. Another is to buffer the HI-6010 inputs near
the chip.
Receiver Seems Dead
After Master Reset the HI-6010 receiver must see a word
gap before the first ARINC data bit.
Error flags must be cleared by either a Status Register
Read or by a Master Reset. The operation of either the
transmitter or the receiver is inhibited upon error.
STATUS BIT
SR0
SR2
SR7
VALUE
0
1
0
1
0
1
Do not load the transmitter buffer
Ready to load the transmitter buffer
Transmission in progress
Transmitter is idle
No transmission error
8 bit mode only error for underwriting data
MEANING
Typically an ARINC