ta1360afg TOSHIBA Semiconductor CORPORATION, ta1360afg Datasheet - Page 14
ta1360afg
Manufacturer Part Number
ta1360afg
Description
Ycbcr/ypbpr Signal And Sync Processor For Digital Tv, Progressive Scan Tv And Double Scan Tv
Manufacturer
TOSHIBA Semiconductor CORPORATION
Datasheet
1.TA1360AFG.pdf
(110 pages)
Available stocks
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Part Number
Manufacturer
Quantity
Price
Part Number:
TA1360AFG
Manufacturer:
TOSHIBA/东芝
Quantity:
20 000
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Bus Control Features
Write Mode
H-FREQ1/2
H-DUTY
YUV-SW
DAC 1
DAC 2
SYNC-SW
HORIZONTAL POSITION
CLP-PHS
ACB MODE
SCP-SW
HBP-PHS1/2
SYNC SEP-LEVEL
TEST
Resister Name
Switches horizontal oscillation frequency. (See the appendix 1)
Switches horizontal output duty.
Switches YUV input.
Switches DAC controlling output.
Controls 1-bit DAC of open-collector when TEST is 00.
Outputs H/C-SYNC from pin 34 when TEST is 01.
Switches DAC controlling output.
Controls 1-bit DAC of open-collector when TEST is 00.
Outputs ACB reference pulse from pin 23 when TEST is 01.
Switches sync input.
Adjusts horizontal picture position (phase).
Note: VP output width (pin 35) varies with a change of horizontal position.
Switches clamp pulse phase.
Also switches CP phase of CP-OUT (pin 47).
Sets ACB mode; Sets converged reference level.
SCP (sand castle pulse) Switches modes.
Switches phase of black-stretch-detection stop pulse.
Leaving Y open and setting the test circuit SW70 to C enable to monitor H/V-BPP
(black-stretch-detection stop pulse) width through pin 70.
Switches Sync SEP-level.
Test Mode:
Controls 1-bit DAC of open-collector when TEST is 00.
Outputs H/C-SYNC from pin 34, and ACB reference pulse from pin 23 when TEST
is 01.
Do not set TEST to 10/11 for that is shipment TEST Mode.
0: 41% 1: 47%
0: INPUT-1 (Y1/C
0: OPEN (high) 1: ON (low)
0: ON (low), 1: OPEN (high)
0: Selects HD/VD input. 1: Selects SYNC input.
0000000: −12.5% 1111111: +12.5%
0: 0.7-µs (2.5%) width, 1.1-µs (3.8%) delay from HD stop phase.
1: 0.7-µs (2.4%) width, 0.2-µs (0.7%) delay from HD stop phase
when no signal, 0.8-µs (2.7%) width that is 1.2-µs (4.2%) delay from FBP start
phase.
00: ACB OFF (cutoff BUS control), 01: ACB ON (5 IRE),
10: ACB ON (10 IRE) 11: ACB ON (20 IRE)
0: Internal Mode 1: External input Mode
HBP-PHS1 = 0 and HBP-PHS2 = 0: FBP ± 3%
HBP-PHS1 = 0 and HBP-PHS2 = 1: FBP ± 8%
HBP-PHS1 = 1 and HBP-PHS2 = 0: FBP ± 13%
HBP-PHS1 = 1 and HBP-PHS2 = 1: FBP ± 18%
00: 16% 01: 24% 10: 32% 11: 40% (At 1125I/60)
b1
/C
r1
) 1: INPUT-2 (Y2/C
14
Description
b2
/C
r2
)
TA1360AFG
33.75 kHz
41%
INPUT-1
OPEN
ON
HD/VD
CENTER
1.1-µs delay
ACB ON
(10 IRE)
Internal Mode
±3%
16%
00
2005-08-18
Preset Value
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