h55s1g32mfp-60 Hynix Semiconductor, h55s1g32mfp-60 Datasheet - Page 48

• Manufacturer Part Number: h55s1g32mfp-60
• Description: 32mx32bit Mobile Sdram
• Manufacturer: Hynix Semiconductor

CM D
C M D
CK
DM
C K
D M
D Q
D Q
Precharge
The Precharge command is used to close the open row in a particular bank or the open row in all banks. When the
precharge command is issued with address A10, high, then all banks will be precharged, and If A10 is low, the open
row in a particular bank will be precharged. The bank(s) will be available when the minimum t
precharge command is issued.
Auto Precharge
The Auto Precharge command is issued to close the open row in a particular bank after READ or WRITE operation. If
A10 is high when a READ or WRITE command is issued, the READ or WRITE with Auto Precharge is initiated.
Burst Termination
The Burst Termination is used to terminate the burst operation. This function can be accomplished by asserting a Burst
Stop command or a Precharge command during a burst READ or WRITE operation. The Precharge command interrupts
a burst cycle and close the active bank, and the Burst Stop command terminates the existing burst operation leave the
bank open.
Data Mask
The Data Mask comamnd is used to mask READ or WRITE data. During a READ operation, When this command is
issued, data outputs are disabled and become high impedance after two clock delay. During a WRITE operation, When
this command is issued, data inputs can't be written with no clock delay.
If data mask is initiated by asserting low on DQM during the read cycle, the data outputs are enabled.
If DQM is asserted to High. the data outputs are masked (disabled) and become Hi-Z state after 2 cycle later. During
the write cycle, DQM mask data input with zero latency
Rev 1.2 / Jun. 2008
R E A D
H i-
H i-
Z
Z
D0
D 0
W RIT
D
D
O U T 0
IN0
W rite Data M asking
R ea d D ata M askin g
D 1
D 1
D 0
D 0
D
Data M asking
M K
O U T1
0 Latency
1Gbit (32Mx32bit) Mobile SDR Memory
D1
D 1
D 0
D 0
D
D
D O T 2
IN2
H55S1G(2/3)2MFP Series
D1
D 1
Data M asking
D0
0 Latency
D 0
D ata M askin g
RP
2 Laten cy
M K
M K
time is met after the
D 1
D 1
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