cx29610 Mindspeed Technologies, cx29610 Datasheet
cx29610
Available stocks
Related parts for cx29610
cx29610 Summary of contents
Page 1
... OptiPHY - M622 STS-12/4x STS-3 SONET/SDH Multiplexer TM CX29610 is a highly integrated, multiport chip that provides SONET/SDH processing and multiplexer/demultiplexer functions for a single STS-12/STM-4 data stream or four STS-3/STM-1 data streams. All mappings are compliant with SONET/SDH standards including Bellcore GR-253, ANSI T1.105, and ITU G.707. ...
Page 2
... Ordering Information Model Number CX29610- PBGA Revision History Document Number 29610-DSH-001-C 29610-DSH-001-B 29610-DSH-001-A © 2004, 2005 Mindspeed Technologies Inc. All Rights Reserved. Information in this document is provided in connection with Mindspeed Technologies (“Mindspeed”) products. These materials are provided by Mindspeed as a service to its customers and may be used for informational purposes only. Mindspeed assumes no responsibility for errors or omissions in these materials ...
Page 3
... MPC860 microprocessor interfaces. A full complement of status monitoring, alarm indications, and error counters is provided with maskable interrupts for all status indications. CX29610 is fully compatible with CX29503 Mindspeed’s Broadband Access Multiplexer (BAM) which is a highly integrated STS-1/DS3/E3/DS1/E1/VT1.5 Mapper/Framer. This chipset ...
Page 4
... Mindspeed Technologies ™ iv ...
Page 5
... CX29610 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 1 ...
Page 6
... Mindspeed Technologies ™ CX29610 CX29610 Data Sheet . . . . . . . . . . . . . . . . . . . . . . . 2-43 29610-DSH-001-C ...
Page 7
... CX29610 CX29610 Data Sheet 2.6.3.2 Basic Operation 2.7 TTL/PECL Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-51 2.7.1 PECL Bias Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-53 2.8 Loopback Modes 2.8.1 Line Loopback 2.8.2 Source Loopback 3.0 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3 ...
Page 8
... Mindspeed Technologies ™ CX29610 CX29610 Data Sheet . . . . . . . . . . . . . . . . . . . 4- 4- 4-32 ...
Page 9
... CX29610 CX29610 Data Sheet hex address:TCCNTL (Tandem Connection Error Counter [Low Byte]) hex address:TXC2 (Transmit C2 Path Overhead Control Register) hex address:TXF1 (Transmit F1 Section Overhead Control Register) hex address:TXF2 (Transmit F2 Path Overhead Control Register) hex address:TXF3 (Transmit Z3/F3 Path Overhead Control Register) hex address:TXK1 (Transmit K1 Overhead Control Register) ...
Page 10
... Appendix A: CX29610 Software Overview A.1 HPI Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-2 A ...
Page 11
... CX29610 Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10 Figure 1-2. CX29610 Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11 Figure 1-3. CX29610 Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12 Figure 1-4. STS-12 Mode Data Flow Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-29 Figure 1-5. 4xSTS-3 Mode Data Flow Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-29 Figure 1-6 ...
Page 12
... PECL to Low Voltage PECL (LVPECL) Interface 5-26 Figure 5-18. CX29610 Ballout Diagram (Top View 5-28 Figure 5-19. CX29610 Ballout Diagram (Bottom View 5-29 Figure 5-20. CX29610 Mechanical Drawing 5-30 Figure A-1. Conceptual Software Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1 ...
Page 13
... Transmit/Receive Configuration: OC-12 Mode, Internal CDR and Transmit Clock Synthesis En- abled 2-14 Table 2-10. Valid Framing Modes for the CX29610 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15 Table 2-11. Default J0/Z0 Transmitted Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16 Table 2-12 ...
Page 14
... Rx8kHz Timing Table 5-20 Table 5-15. E1/E2 Timing Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-21 Table 5-16. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-22 Table 5-17. DC Characteristics 5-23 Table 5-18. PECL—Input Characteristics 5-24 Table 5-19. PECL—Output Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-24 Table 5-20. Single-ended PECL Table 5-24 Table 5-21. Listing of Pin Numbers and Labels (Numeric Order 5-31 xiv Mindspeed Technologies ™ CX29610 CX29610 Data Sheet 29610-DSH-001-C ...
Page 15
... STS-1 SPEs to STS-3 or STS-12 formatted data streams. It operates as a single STS-12 to STS-1 multiplexer four-port (quad) STS-3 to STS-1 multiplexer. The CX29610 integrates a full SONET/SDH overhead processor, which generates and terminates the STS-12 and/or STS-3 section, line, and path octets. The following features are also provided: • ...
Page 16
... Product Description 1.1 CX29610 Features 1.1.1 General System Features The CX29610 provides the following general system features: • An 8-bit microprocessor interface that supports the Mindspeed EBUS • A one-second input, with a one-second output derived from an 8 kHz clock • A power down control is provided for each STS-3 port in the 4x STS-3 • ...
Page 17
... CX29610 CX29610 Data Sheet 1.1.3 Receiver Features The CX29610 provides the following receiver features: • De-maps STS-1 SPEs from STS-3 or STS-12 frame structures. • Terminates section, line, and path overhead layers and reports errors and • A serial LVPECL interface to external transceiver devices for STS-12 • ...
Page 18
... Product Description 1.1 CX29610 Features 1.1.3.1 Alarm/Error • LOS—loss of signal. The incoming signal is monitored for an all-zeros or Detection and Performance Monitoring Features • LOP-P—loss of pointer. The H1/H2 pointer processor reports LOP in bit 7 • AIS-L—Line AIS is reported in RXLIN bit 6 when bits 6, 7, and 8 of the • ...
Page 19
... When an LOP tandem connection ISF defect is detected on the • Capability of generating AIS-P on reception of PLM-P or Uneq-P is 1.1.4 Diagnostic Features The CX29610 provides the following diagnostic features: • Source loopback is provided by connecting the line-side transmit clock • Line loopback is provided by connecting the receive data inputs (before • ...
Page 20
... Conventions The signal direction naming used in this specification is Transmit when data is flowing from the slave devices to the CX29610 and Receive when data is flowing from the CX29610 to the slave devices. All signals are active high, unless denoted via a trailing “*” after the signal name, for example (or _n) following the a pin label indicates the port number (1– ...
Page 21
... CX29610 CX29610 Data Sheet 1.4 Terminology The synchronous digital hierarchy (SDH) is the international counterpart to the synchronous optical network (SONET) used in the United States, Canada, and Japan. As such, SDH and SONET use different terminology to express similar concepts. Table 1-3 Table 1-3. SONET/SDH Terminology VT Payload VT Synchronized ...
Page 22
... Section Overhead All frame overhead is considered the same in SDH pending further definition. Synchronous Basic framing for time division multiplexing in an Transport Module essentially circuit oriented hierarchy. (STS) (STM) STS-3 = STM-1. Mindspeed Technologies ™ CX29610 CX29610 Data Sheet Definition 29610-DSH-001-C ...
Page 23
... There are 95 power and 33 ground pins. Pin descriptions are given in NOTE: 29610-DSH-001 logic diagram of the CX29610’s functional blocks. There are four An asterisk (*) following a pin label indicates that the pin logic level is active low, and an _# following the a pin label indicates the port number (1– ...
Page 24
... Product Description 1.5 Logic Diagram Figure 1-1. CX29610 Logic Diagram One-Second Clock Sync I Reset I 8 kHz Ref. Clock Input I Transmit Clock Input I External RC Network I External RC Network I Transmit Frame Input I Transmit Section DCC Input I Transmit Line DCC Input I Local Oscillator Reference I External Resistor I Local Oscillator Reference I NOTE(S): Only port 1 is used in the Line side STS-12/STM-4 mode ...
Page 25
... CX29610 CX29610 Data Sheet Figure 1-2. CX29610 Logic Diagram LSigDet_1 LSigDet_2 Signal Detection I LSigDet_3 LSigDet_4 LRxClk+/–_1 LRxClk+/–_2 Receive Clock Input I LRxClk+/–_3 LRxClk+/–_4 LRxData+/–_1 LRxData+/–_2 Receive Data Input I LRxData+/–_3 LRxData+/–_4 LRxPFP_1 LRxPFP_2 External RC Network I LRxPFP_3 ...
Page 26
... Product Description 1.5 Logic Diagram Figure 1-3. CX29610 Logic Diagram Bus Mode Select I Processor Clock I Read/Write Control I Read Control I Transfer Start I Chip Select I Address Bus I Internal Scan Control I Test Reset I Test Clock I Test Mode Select I Test Data Input I SIBus Transmit Parity Input I SIBus Transmit Data I NOTE(S): Only port 1 is used in the Line side STS-12/STM-4 mode ...
Page 27
... CX29610 CX29610 Data Sheet Pin names are listed in indicates that the pin logic level is active low, and an _# following the a pin label indicates the port number (1-4). Refer to by pin number. Table 1-4. Pin Definitions (1 of 16) Pin Label Signal Name OneSecIn One Second Input ...
Page 28
... Diff I PECL AC1 Diff I PECL Mindspeed Technologies ™ CX29610 CX29610 Data Sheet Description Transmit frame reference input Transmit section DCC data input Transmit line DCC data input Local oscillator reference External resistor connection for receive CDR Local oscillator reference (19.44 MHz). This pin is high when the LIU is receiving a valid signal ...
Page 29
... CX29610 CX29610 Data Sheet Table 1-4. Pin Definitions (3 of 16) Pin Label Signal Name LRxClk+_1 Line Receive Clock Positive LRxClk+_2 LRxClk+_3 LRxClk+_4 LRxData–_1 Line Receive Input Negative LRxData–_2 LRxData–_3 LRxData–_4 LRxData+_1 Line Receive Input Positive LRxData+_2 LRxData+_3 LRxData+_4 LRxPFP_1 ...
Page 30
... AC6 TTL O C5 TTL O Mindspeed Technologies ™ CX29610 CX29610 Data Sheet Description Complement of the above PECL Line Transmit Data. 622.08/155.52 MHz output derived from one of three clock sources: transmit clock synthesizer, recovered receive clock or the LTxClkI+/- Input. The clock source is selected in bits 3 and 4 of the CLKREC register ...
Page 31
... CX29610 CX29610 Data Sheet Table 1-4. Pin Definitions (5 of 16) Pin Label Signal Name RxTstClk_1 Receive 19.44 MHz Clock Output RxTstClk_2 RxTstClk_3 RxTstClk_4 RxFrameOut_1 Receive Frame Reference Output RxFrameOut_2 RxFrameOut_3 RxFrameOut_4 RxSDCC_Clk_1 Receive Section DCC Clock Output RxSDCC_Clk_2 RxSDCC_Clk_3 RxSDCC_Clk_4 RxSDCC_Dat_1 Receive Section DCC ...
Page 32
... C17 TTL O B16 TTL O D17 TTL O Mindspeed Technologies ™ CX29610 CX29610 Data Sheet Description Data to be transmitted in the SONET/SDH E2 octet may be input serially on this pin. See Section 5.1.10. Provides frame sync indication for the RxE1/RxE2 and TxE1/TxE2 inputs and outputs. See Section 5.1.10. ...
Page 33
... CX29610 CX29610 Data Sheet Table 1-4. Pin Definitions (7 of 16) Pin Label Signal Name MMode Processor Interface Selection MClk Microprocessor Clock MRW* Microprocessor Read/Write Control MRD* Microprocessor Read Control MTS* Microprocessor Transfer Start MCS* Microprocessor Chip Select MA[10] Microprocessor Address Bus MA[9] MA[8] MA[7] MA[6] MA[5] MA[4] MA[3] MA[2] MA[1] MA[0] 29610-DSH-001-C (1) No. Type ...
Page 34
... I pull-up B5 TTL O Mindspeed Technologies ™ CX29610 CX29610 Data Sheet Description When a logic “0” is read on this pin, the device needs servicing. It remains asserted until the pending interrupt is acknowledged. This pin is an open drain output for an external wired “OR” logic implementation. ...
Page 35
... CX29610 CX29610 Data Sheet Table 1-4. Pin Definitions (9 of 16) Pin Label Signal Name STxPrty_1 SI-Bus Transmit Parity Input STxPrty_2 STxPrty_3 STxPrty_4 29610-DSH-001-C (1) No. Type I/O C20 TTL I E26 TTL I M25 TTL I Y25 TTL I Mindspeed Technologies ™ 1.0 Product Description 1.5 Logic Diagram Description Odd parity calculated over STxData[7:0] ...
Page 36
... Y24 TTL I Y26 TTL I Mindspeed Technologies ™ CX29610 CX29610 Data Sheet Description SI-Bus Port 1 transmit data from the slave device. SI-Bus Port 2 transmit data from the slave device. SI-Bus Port 3 transmit data from the slave device. SI-Bus Port 4 transmit data from the slave device ...
Page 37
... CX29610 CX29610 Data Sheet Table 1-4. Pin Definitions (11 of 16) Pin Label Signal Name STxHSClk_1 SI-Bus High Speed Transmit Clock STxHSClk_2 STxHSClk_3 STxHSClk_4 STxClk_1 SI-Bus Transmit Clock STxClk_2 STxClk_3 STxClk_4 STxStart_1 SI-Bus Transmit Start STxStart_2 STxStart_3 STxStart_4 SRxHSClk_1 SI-Bus HS Receive Clock SRxHSClk_2 SRxHSClk_3 ...
Page 38
... U24 TTL O T25 TTL O U23 TTL O U26 TTL O AB25 TTL O AC26 TTL O AC24 TTL O AC25 TTL O AD26 TTL O AE24 TTL O AE26 TTL O AF25 TTL O Mindspeed Technologies ™ CX29610 CX29610 Data Sheet Description SI-Bus Port 1 receive data sent to the slave device. 29610-DSH-001-C ...
Page 39
... CX29610 CX29610 Data Sheet Table 1-4. Pin Definitions (13 of 16) Pin Label Signal Name SRxPrty_1 SI-Bus Receive Parity SRxPrty_2 SRxPrty_3 SRxPrty_4 VDD Digital Power 29610-DSH-001-C (1) No. Type I/O A25 TTL O K23 TTL O V24 TTL O AD25 TTL O D7 — D11 D16 D20 G23 L23 T23 ...
Page 40
... AA3 AB3 AC3 C7 — Mindspeed Technologies ™ CX29610 CX29610 Data Sheet Description 3.3 V analog power supply Provides Electrostatic Discharge (ESD) protection and over voltage protection. When the device is used with 5 V devices on the board, tie this pin for 5 V signal tolerance. Otherwise, tie to 3 ...
Page 41
... CX29610 CX29610 Data Sheet Table 1-4. Pin Definitions (15 of 16) Pin Label Signal Name VSS Digital Ground 29610-DSH-001-C (1) No. Type I/O A26 — B25 C24 D13–D14 D18 D23 J23 K10–K17 L11–L17 M12–M17 N12–N17 N23 P12–P17 P23 R12–R17 T11– ...
Page 42
... L10 M10–M11 N3 N10–N11 P3–P4 P10–P11 R10–R11 T10 W4 AC4 AD3 AE2 AF1 D3 — AB4 AE3 AF2 Mindspeed Technologies ™ CX29610 CX29610 Data Sheet Description These pins are ground connections. These pins are reserved and must be left unconnected. 29610-DSH-001-C ...
Page 43
... CX29610 CX29610 Data Sheet 1.6 Block Diagram and Descriptions The CX29610 can be used to multiplex and de-multiplex SONET STS-1 SPEs from an interleaved bus format (Mindspeed SI-Bus) to STS-3 or STS-12 formatted data streams. The device can be operated as a single STS-12 to STS-1 demultiplexer quad STS-3 to STS-1 demultiplexer. Data flow diagrams are shown for the STS-12 and 4xSTS-3 modes in respectively ...
Page 44
... The SONET Interleave Bus (SI-Bus) is defined in access to configuration, status and counter registers. 1-30 Tx Overhead Micro Control Bits Generation Pointer Processor Rx Overhead Micro Status/Counters Termination Section 2.5. An 8-bit microprocessor interface provides Mindspeed Technologies ™ CX29610 CX29610 Data Sheet Payload Generate Payload Locate 100518_010 29610-DSH-001-C ...
Page 45
... Functional Description This chapter describes the CX29610 architecture and functional blocks. Figure 2-1 Figure 2-1. CX29610 Block Diagram Tx Frame Sync In/Out STS3/12 Tx Framer Line Interface/ CDR STS3/12 Rx Framer Rx8kHz Rx Frame Sync Out 29610-DSH-001-C 2 shows the CX29610’s transmit and receive signal path. Tx Overhead ...
Page 46
... The CX29610 communicates with the external SONET/SDH network through its line interface, which can connect to a optical trasnceiver enabling transmission over a fiber optic cable. The CX29610 recovers a receive clock from the incoming receive data via an onboard PLL circuit. The receive PLL requires a 19 ...
Page 47
... CX29610 CX29610 Data Sheet 2.1.1 Transmit and Receive PLL Filter Networks External filter networks are required by the transmit and receive Phase Locked Loop (PLL) as shown in to the device as possible. Figure 2-2. PLL Bias Network 29610-DSH-001-C Figure 2-2. These components should be located as close 15.4/68.1 R1 LRXPFP 1500 pF ...
Page 48
... Line Interface 2.1.2 Signal Detect Interface The LSigDet pin on the CX29610 indicates when the PMD has lost its signal. If the LSigDet goes low, the CX29610 internally forces its receive data to logic ‘0’ to prevent false framing indications. Designs that do not use the LSigDet input must tie this pin high and then ensure that they either externally force the receive data to a logic ‘ ...
Page 49
... CX29610 CX29610 Data Sheet 2.2 Clock Circuits The CX29610 has four transceiver blocks comprised of a PECL interface, a CDR circuit, a serial to parallel, and a parallel to serial circuit as shown in One transmit synthesizer circuit generates a transmit line clock for all four ports. The transceiver and synthesizer blocks operate at OC-12 (622 Mbps) for port one and OC-3 (155 Mbps) for all four ports ...
Page 50
... Functional Description 2.2 Clock Circuits Figure 2-5. Receive Clock Generation and Data Path 2-6 Mindspeed Technologies ™ CX29610 CX29610 Data Sheet 500243_002a 29610-DSH-001-C ...
Page 51
... CX29610 CX29610 Data Sheet Figure 2-6. Transmit Clock Generation and Data Path 29610-DSH-001-C Mindspeed Technologies ™ 2.0 Functional Description 2.2 Clock Circuits 500243_001a 2-7 ...
Page 52
... Functional Description 2.2 Clock Circuits The line interface circuits of the CX29610 provide many clock and data path selections for loopback capabilies. The available loopback modes are described in Section Table 2-3 of the the line interface for the OC-12 SONET mode. This is the default mode of operation upon device reset. The control registers shown in Table 2-3 ...
Page 53
... CX29610 CX29610 Data Sheet The transmit section synthesizes the 155.52/622.08 MHz clock used for transmitting data from one of four sources based on the control bits TxClkSel[1:0] in the CLKREC register as shown in Table 2-4. TxClkSel[1:0] Control Bits TxClkSel1 The receiver section uses an internal Phase Locked Loop (PLL) to recover the clock from the incoming NRZ data stream ...
Page 54
... Table 2-6. Category II Jitter Transfer Mask OC/STS Level f (Hz 130 12 500 Table 2-7. CX29610 Jitter Specification Parameter Jitter Generation (Tx Output) Jitter Generation Jitter Generation (loopback from Rx to Tx) Adjacent Channel Isolation Rise/Fall Time 2.2.1 Loss of Lock When the CDR determines that a Loss of Lock (also referred Loss of Synchronization) has occurred, it asserts the Loss of Lock (LOL) bit in the RXSEC register and the LOL bit in the SECINT register ...
Page 55
... CX29610 CX29610 Data Sheet 2.3 Device Configuration and Setup The following information illustrates how to configure the CX29610 for various SONET and SDH operating modes. The device can operate in either a OC-12/STM 4xOC-3/STM-1 configuration. The device has four sets of registers for each physical line port (1-4) when operating in the 4xOC-3/STM-1 mode. When operating in the OC-12/STM-4 mode, with only one physical line port active (i.e., port 1), registers labeled as ports 2– ...
Page 56
... Functional Description 2.3 Device Configuration and Setup Figure 2-8. Default Clock and Data Receive Path 2-12 Mindspeed Technologies ™ CX29610 CX29610 Data Sheet 500243_002a 29610-DSH-001-C ...
Page 57
... CX29610 CX29610 Data Sheet Figure 2-9. Default Clock and Data Transmit Path 29610-DSH-001-C Mindspeed Technologies ™ 2.0 Functional Description 2.3 Device Configuration and Setup 500243_001a 2-13 ...
Page 58
... Device Configuration and Setup Table 2-9 of the line interface for the OC-12 SONET mode. The line interface circuits of the CX29610 provide many clock and data path selections for loopback capabilies. The available loopback modes are described in Section Table 2-9. Transmit/Receive Configuration: OC-12 Mode, Internal CDR and Transmit Clock Synthesis Enabled ...
Page 59
... The GEN register selects the mapping format for the CX29610. The PrtMode bit configures the device as either four independent STS-3/STM-1 ports or a single STS-12/STM-4. (The SI-Bus is always four independent OC-3/STM-1 data streams.) The FrmMode bit selects between SONET and SDH framing modes. This ...
Page 60
... Bit AU port 1 STM-4 AUG . . x3 . port 4 AU-3 AUG Internal to the CX29610 External to the CX29610 NOTE(S): The default values for H1/H2 are 0x620A. This indicates that the J1 path overhead byte is located immediately after the Z0 octets. 2-16 Transmitted Values Z0-4 Z0-5 Z0-6 Z0-7 Z0-8 — — — — — ...
Page 61
... CX29610 CX29610 Data Sheet Figure 2-11. AU-3 Basic Frame (STM AUG AU-3 Mapping) Row A1-1 A1-2 A1-3 1 A1/A2 port 1 A1/A2 port 1 A1/A2 port port SDCC port H1-1 H1-2 H1-3 TxPntr port 1 TxPntr port 2 TxPntr port 3 4 path 1 path 1 path 1 5 B2-1 B2-2 B2-3 InsB2Err1 port 1 InsB2Err1 port 2 InsB2Err1 port 3 ...
Page 62
... Gen Register 0x000 PrtMode FrmMode AU4Mode Bit 7 Bit 6 Bit AU-4 x4 port 1 x1 STM-4 AUG . . x3 . port 4 AU-3 AUG Internal to the CX29610 External to the CX29610 2-18 TU3Mode Bit 4 0 TUG-2 to TUG-3 to AU-4 VC TUG-3 x7 VC-3 x7 TUG-2 x4 Mindspeed Technologies ™ CX29610 CX29610 Data Sheet C-4 139.264 Mbps ...
Page 63
... CX29610 CX29610 Data Sheet Figure 2-13. STM-4 to TUG-2 Row A1-1 A1-2 A1-3 A1/A2 port 1 A1/A2 port 1 A1/A2 port port SDCC port H1-1 H1-2 H1-3 4 TxPntr port 1 TxPntr port 2 TxPntr port 3 path 1 path 1 path 1 5 B2-1 B2-2 B2-3 InsB2Err1 port 1 InsB2Err1 port 2 InsB2Err1 port LDCC port ...
Page 64
... Functional Description 2.4 SONET/SDH Framer and Overhead Processor Figure 2-14. STS-4–STS-12 Gen Register 0x000 PrtMode FrmMode AU4Mode Bit 7 Bit 6 Bit OC-12 2-20 TU3Mode Bit 3 0 SONET OC-12 OC-3 OC-3 OC-3 OC-3 Mindspeed Technologies ™ CX29610 CX29610 Data Sheet 100518_051 29610-DSH-001-C ...
Page 65
... PrtMode FrmMode AU4Mode Bit 7 Bit 6 Bit AU port 1 STM-N AUG . . . x3 port 4 AU-3 AUG Internal to the CX29610 External to the CX29610 29610-DSH-001-C 2.4 SONET/SDH Framer and Overhead Processor TU3Mode Bit 4 1 TU-3 to TUG-3 to AU-4 VC TUG-3 x7 VC-3 x7 TUG-2 x4 Mindspeed Technologies ™ 2.0 Functional Description C-4 139.264 Mbps TU-3 ...
Page 66
... Mindspeed Technologies CX29610 CX29610 Data Sheet A1-8 A1-9 A1-10 A1-11 A1-12 A1/A2 port 1 A1/A2 port 1 A1/A2 port 1 A1/A2 port B2-8 B2-9 B2-10 B2-11 B2-12 InsB2Err3 port 1 ...
Page 67
... Overhead block and provides status bits to the SONET Overhead processor for presentation in status registers. The SONET Overhead block uses defined overhead bytes in an STS-3/STM-1 frame for Performance Monitoring, Fault Management, and Facility Testing. the CX29610 uses. Table 2-12. SONET Overhead Byte Definitions and Values ( Layer Byte ...
Page 68
... RXSEC bit 5. LOS is cleared when two consecutive valid framing patterns with no intervening all-zeros pattern have been received. NOTE: 2-24 Function A low level input on the SigDet pin causes the CX29610 to clamp the input data to all zeroes, forcing an LOS alarm. Mindspeed Technologies ™ CX29610 ...
Page 69
... A1, A2 Severely In normal operation, the A1 and A2 bytes contain F6h and 28h respectively, and Errored Frames (SEF) are used by the CX29610 to determine the location of a frame within a data stream. The STS-3/STM-1 framing bytes, A1 and A2, are monitored for SEF conditions. SEF is declared if errors are detected in four consecutive frames. A SEF condition causes the SEF bit in the RXSEC register to be set high and the SEFCNT register to be incremented ...
Page 70
... Mindspeed Technologies ™ CX29610 CX29610 Data Sheet illustrates this. State of the J1 buffer after the 64th frame 100518_029 ...
Page 71
... CX29610 CX29610 Data Sheet 2.4.2.4 B1 The B1 octets are allocated for section layer monitoring and contain a Bit Interleaved Parity (BIP-8) code. An error causes the B1Err bit in RXSEC to be set high and increments the B1CNT registers. On the transmit side, the B1 octet contains the BIP-8 calculation by default. ...
Page 72
... From the TXZ2a/TXZ2b registers Line FEBE inserted From the TxE2 pin Undefined overhead positions carry 00h. Mindspeed Technologies ™ CX29610 CX29610 Data Sheet Receive Full GR.253 pointer processor Used for negative justification Checked, errors counted Checked, interrupt on change External serial access ...
Page 73
... CX29610 CX29610 Data Sheet 2.4.3.3 Loss of Pointer The H1and H2 pointer processor reports Loss of Pointer (LOP) in RXPTH bit valid pointer is not found for 10 consecutive frames. LOP-P is cleared when a valid pointer with NDF or a valid concatenation indicator has been received for three consecutive frames. LOP-P is terminated upon detection of AIS-P or when relaying an all-ones pointer ...
Page 74
... APSTHRESH register, then signal degrade or signal fail status will be reported in RXAPS bits respectively. The CX29610 can detect BERs in the range 10 exponent into a control register. The circuitry configures observation window lengths and error count thresholds directly from the programmed BER exponent. ...
Page 75
... The tightest requirement is at the 10 Table 2-17 requirements for the STS-12 rate that is needed for CX29610. At the STS-12 rate, the Line BIP (B2) covers 9612 octets or 76,896 bits per STS-12 frame. Since the data rate is higher, fewer frames need to be observed to estimate the BER; but the same observation windows can’ ...
Page 76
... Mindspeed Technologies ™ CX29610 CX29610 Data Sheet K2 bits 111 110 for a minimum of 20 frames. 110 for a minimum of 20 frames upon detection of LOS, LOF, or AIS-L. From TXK2 bits when no LOS, LOF, or AIS-L detected. From TXK2 bits ...
Page 77
... CX29610 CX29610 Data Sheet 2.4.3.16 S1 The Synchronization Status byte, S1, indicates the signal clock quality and clock source. S1 carries the value from the TXS1 register. The S1 byte is latched into the RXS1 register. A maskable interrupt (LININT bit 2) will be generated when the incoming S1 byte differs consistently from the current value for 8 consecutive frames ...
Page 78
... The E2 byte is latched from the receive stream and then shifted out to the RxE2 output pin. 2.4.4 Path Overhead Path overhead can either be generated by CX29610 or taken from the path overhead presented in the STS-1 inputs from the SI-Bus interface. Internal generation is the default, but each overhead octet can be individually selected as either internally generated or sourced from the SI-Bus interface by the bits in the PTHINS register ...
Page 79
... CX29610 CX29610 Data Sheet 2.4.4.3 C2 The Path Signal label byte, C2, identifies the type of payload being received. C2 carries the value from the SI-Bus as the default. If PTHINSL bit 5 is high, then C2 will contain the contents as received on the SI-Bus interface. The C2 byte is latched into the RXC2 register after consistent values are received for 5 consecutive frames ...
Page 80
... Trigger 1 LOS, LOF, AIS-L, AIS-P, LOP-P 1 UNEQ-P 1 PLM defects Mindspeed Technologies ™ CX29610 CX29610 Data Sheet G1 bits 101 for a minimum of 20 frames. 110 for a minimum of 20 frames. 010 for a minimum of 20 frames. 001 for a minimum of 20 frames. 29610-DSH-001-C ...
Page 81
... CX29610 CX29610 Data Sheet 2.4.5 Custom Extensions Several of the control register bits in the CX29610 register map are for specific applications when CX29610 is used with the Broadband Access Mapper (BAM) device. These bits may be of use in other applications but may also generate operation that does not conform to SONET standards. This is not a problem when used with BAM, since BAM is a termination device and thus the non-standard data contained is only visible between CX29610 and BAM ...
Page 82
... The VER register (0x03) uniquely identifies the device and revision level. 2.5.3 Counters The CX29610 counters are used to record events within the device. There are two types of events: error events, such as Section BIP errors, and transmission events. Counters which are composed of more than one register must be accessed by reading the least significant byte first ...
Page 83
... The CX29610 implements one-second latching for both status signals and counter values. When EnStatLat (bit 5) in the GEN register is written to a logic 1, a read from any of the status registers will return the state of the device at the time of the previous OneSecIn pin assertion ...
Page 84
... Interrupt Indication Status Register Register — SUMINT — PORTINT RXSEC SECINT RXLIN LININT RXAPS APSINT RXPTH_n PTHINT_n PNTRSTAT_n PNTRINT_n illustrates the interrupt hierarchy. Mindspeed Technologies ™ CX29610 CX29610 Data Sheet Interrupt Enable Register ENSUMINT ENPORTINT ENSEC ENLIN ENAPS ENPTH_n ENPNTR_n 29610-DSH-001-C ...
Page 85
... CX29610 CX29610 Data Sheet Figure 2-18. Interrupt Hierarchy Port 4 SigDetInt B1ErrInt SecTraceInt K1K2Int AIS-LInt RDI-LInt B2ErrInt REI-LInt PSBFInt SigFailInt SigDegradeInt Port 1 SigDetInt B1ErrInt SecTraceInt K1K2Int AIS-LInt RDI-LInt B2ErrInt REI-LInt APSINT 0x03E RXAPS PSBF PSBFInt 2 2 AND SigFail ...
Page 86
... Functional Description 2.5 Microprocessor Interface The CX29610’s interrupt indications can be classified as either single-event or dual-event. A single-event interrupt is triggered by a status assertion. A dual-event interrupt is triggered by either a status assertion or deassertion. Both types of interrupts are further described in the following examples. All interrupt bits have a corresponding enable bit. This allows software to disable or mask interrupts as required ...
Page 87
... LOS condition results in almost all other interrupts being set, even Conditions though only the LOS condition needs to be addressed by software. To help simplify the software interrupt routines, the CX29610 automatically supresses higher-level interrupt when the errors shown in Table 2-24. Interrupt Suppression during Error Conditions ...
Page 88
... The SI-Bus interface is capable of full-duplex, bi-directional transmission of SONET(SDH) data between a CX29610 device and several slave devices. By definition, receive data flows from the CX29610 to the slave and transmit data flows from the slave to the CX29610. Clocks and alignment controls flow from the CX29610 to the slave in both the transmit and receive directions. ...
Page 89
... Nominal rate is 51.84 MHz. The clock signal is generated by the CX29610 and supplied to the slave. Nominal rate is 19.44 MHz. The 8-bit data path for transmit data from the slave device to the CX29610 device. TxData[7] is the MSB, TxData[0] is the LSB. Data is provided in response to the TxClk signal. ...
Page 90
... Figure 2-19. SI-Bus Clock Relationships 155.52 MHz Clock Edges TxHSClk/RxHSClk (51.84 MHz) TxClk/RxClk (19.44 MHz) Data Transfer (e.g. TxStart) 2-46 Each port (1–4) of the CX29610 is an independent master for its own SI-Bus. Figure 2-19 illustrates the relationship of the clock Mindspeed Technologies ™ CX29610 CX29610 Data Sheet 100518_017 29610-DSH-001-C ...
Page 91
... Basic Operation Data transfer can be between three slave devices (or a multi-channel slave device) and the CX29610 and involves the transfer of three interleaved STS-1 frames across the data bus. The Start signals indicate the beginning of the STS-1 frame (A1 octet) and are one octet clock in duration. ...
Page 92
... Figure 2-21 CX29503 devices. The "_n" suffixes on the CX29610 signal names range from 1–4 and indicate the four SI-Bus interfaces on the CX29610. The set of signals for each SI-Bus interface must connect to the same CX29503 device. For example, STxHSClk_1, STxClk_1, etc. must connect to the same CX29503 device ...
Page 93
... TxClk. expects to sample the A1 octet position (first octet of the STS frame) on the clock edge (2) after the TxStart signal is provided (edge 1). The CX29610 device samples data on every TxClk edge, with 2430 clock edges defining the 3 interleaved STS-1 frames. Each slave device responds on every third TxClk edge and is three-stated during the intervening two TxClk cycles ...
Page 94
... Functional Description 2.6 SI-Bus Interface The CX29610 device generates RxHSClk, RxClk, RxStart[3:1], and RxData Receive Interface signals to control the slave devices. The RxStart[3:1] and RxData signals are provided synchronously with the rising edge of RxClk. these data relationships. Each RxStart signal indicates the position of the A1 octet in the STS-1 frame that corresponds to its number ...
Page 95
... CX29610 CX29610 Data Sheet 2.7 TTL/PECL Interface The LSigDet pin on the CX29610 line interface can be driven by TTL or PECL drivers. The CX29610 can be connected directly to a TTL interface without external components. When using a single-ended PECL interface, the input signal must be centered around V A typical LIU/PECL interface is shown in assumes a 3 ...
Page 96
... Functional Description 2.7 TTL/PECL Interface 2.7.1 PECL Bias Network The CX29610 can utilize a new PECL bias network as shown in This simplifies board layout by eliminating the pull-up resistors used in previous PECL interfaces. The CX29610 is backward compatible with legacy layouts as shown in All PECL traces must be treated as transmission lines. Therefore, standard high-speed practices must be followed: • ...
Page 97
... CX29610 Data Sheet 2.8 Loopback Modes Loopbacks are diagnostic tools used to verify the data path. The CX29610 has two loopback modes: Line Loopback (which checks the line between a remote device and the PHY) and Source Loopback (which checks that the host (the SI-Bus) is communicating with the PHY) ...
Page 98
... Loopback Modes 2.8.2 Source Loopback Source loopback is enabled and disabled in bit 1 the CLKREC register. When source loopback is enabled, all data transmitted by the CX29610 is also looped back through the Receive Line Interface. Data from the LIU is ignored. Figure 2-27. Source Loopback Diagram STS-12/STM-4 ...
Page 99
... CX29610 CX29610 Data Sheet Figure 2-28. Line Loopback—Receive 29610-DSH-001-C Mindspeed Technologies ™ 2.0 Functional Description 2.8 Loopback Modes 500243_002b 2-55 ...
Page 100
... Functional Description 2.8 Loopback Modes Figure 2-29. Line Loopback—Transmit 2-56 Mindspeed Technologies ™ CX29610 CX29610 Data Sheet 500243_001b 29610-DSH-001-C ...
Page 101
... CX29610 CX29610 Data Sheet Figure 2-30. Local Source Loopback—Receive 29610-DSH-001-C Mindspeed Technologies ™ 2.0 Functional Description 2.8 Loopback Modes 500243_002c 2-57 ...
Page 102
... Functional Description 2.8 Loopback Modes Figure 2-31. Local Source Loopback—Transmit 2-58 Mindspeed Technologies ™ CX29610 CX29610 Data Sheet 500243_001c 29610-DSH-001-C ...
Page 103
... CX29610 CX29610 Data Sheet Figure 2-32. Source Loopback—Receive 29610-DSH-001-C Mindspeed Technologies ™ 2.0 Functional Description 2.8 Loopback Modes 500243_002d 2-59 ...
Page 104
... Functional Description 2.8 Loopback Modes Figure 2-33. Source Loopback—Transmit 2-60 Mindspeed Technologies ™ CX29610 CX29610 Data Sheet 500243_001d 29610-DSH-001-C ...
Page 105
... Applications The CX29610 is targeted for network edge applications where SONET OC-12/OC-3 or SDH STM-4/STM-1 traffic is terminated for STS-1 payload processing. For HDLC processing applications, Mindspeed's CX28560 interfaces to the CX29610 for processing of 2,047 HDLC channels. Typical applications are illustrated in 29610-DSH-001-C 3 Figures 3-1 and 3-2. Mindspeed Technologies ™ ...
Page 106
... OC-12/STM-4 Path Termination for HDLC Application 3.1 OC-12/STM-4 Path Termination for HDLC In the OC-12/STM-4 application, four CX29503 Broadband Access Multiplexer devices are used with a single CX29610 OC-12 SONET/SDH Multiplexer, and one CX28560 2,047 HDLC controller. This application allows for a termination of tributary signals down to DS1/E1. ...
Page 107
... CX29610 Data Sheet 3.2 OC-3/STM-1 Path Termination for HDLC In the OC-3/STM-1 application, one CX29503 Broadband Access Multiplexer is used with a single OC-3 channel of the CX29610 SONET/SDH Multiplexer and one CX28560 2,047 Channel HDLC controller. This application allows for a termination of tributary signals down to DS1/E1. Figure 3-2. OC-3/STM-1 Full DS0/E0 Channelization Application ...
Page 108
... Applications 3.2 OC-3/STM-1 Path Termination for HDLC Application 3-4 Mindspeed Technologies ™ CX29610 CX29610 Data Sheet 29610-DSH-001-C ...
Page 109
... Registers 4.1 Memory Map The CX29610 memory space consists of 2048 bytes divided into 5 sections as shown in Table 4-1. Port Register Address Sections Address 0x000-00D 0x010-170 0x210-370 0x410-570 0x610-770 The control/status register name assignments are the same for each port and are shown in the individual control bits are different between port 1 and the other ports due to the dual function of port 1 for STS-3 and STS-12 formats ...
Page 110
... Status Output Control Register — Reserved R/W — Clock Recovery/Power Down Control Register CLKREC R/W — Clock Recovery/Loopback Control Register Mindspeed Technologies ™ CX29610 CX29610 Data Sheet Figure 1-4 and Page Description Number page 4-28 page 4-35 page 4-17 page 4-41 page 4-26 page 4-58 page 4-70 page 4-58 page 4-71 page 4-71 ...
Page 111
... CX29610 CX29610 Data Sheet Table 4-2. Processor Memory Map (2 of 12) Address Port 1 Port 2 Port 3 Port 4 0x015 0x215 0x415 0x615 0x016 0x216 0x416 0x616 0x017 0x217 0x417 0x617 0x018 0x218 0x418 0x618 ENPORTINT 0x019 0x219 0x419 0x619 0x01A 0x21A 0x41A 0x61A 0x01B 0x21B ...
Page 112
... Counters Section BIP Error Counter (high byte) Reserved Reserved B2CNTL R Counters Line BIP Error Counter (low byte) B2CNTM R Counters Line BIP Error Counter (mid byte) Mindspeed Technologies ™ CX29610 CX29610 Data Sheet Page Description Number page 4-55 page 4-55 page 4-26 page 4-22 page 4-22 page 4-56 page 4-29 page 4-14 ...
Page 113
... CX29610 CX29610 Data Sheet Table 4-2. Processor Memory Map (4 of 12) Address Port 1 Port 2 Port 3 Port 4 0x052 0x252 0x452 0x652 0x053 0x054 0x254 0x454 0x654 0x055 0x255 0x455 0x655 0x056 0x255 0x455 0x655 0x057 0x058 0x258 0x458 0x658 TXSECBUF 0x059 0x259 0x459 0x659 ...
Page 114
... Counters REI-P Error Counter (high byte) for Path 1 R Counters Tandem Conn. Error Counter (low byte) for Path 1 R Counters Tandem Conn. Error Counter (high byte) for Path 1 Mindspeed Technologies CX29610 CX29610 Data Sheet Page Description Number page 4-23 page 4-40 page 4-32 page 4-51 page 4-50 ...
Page 115
... CX29610 CX29610 Data Sheet Table 4-2. Processor Memory Map (6 of 12) Address Port 1 Port 2 Port 3 Port 4 0x0A6 0x2A6 0x4A6 0x6A6 0x0A7 0x2A7 0x4A7 0x6A7 NDFCNT-1 0x0A8 0x2A8 0x4A8 0x6A8 PJCNTL-1 0x0A9 0x2A9 0x4A9 0x6A9 PJCNTH-1 0x0AA 0x2AA 0x4AA 0x6AA NJCNTL-1 0x0AB 0x2AB 0x4AB ...
Page 116
... Counters BIP Error Counter (high byte) for Path 2 R Counters REI-P Error Counter (low byte) for Path 2 R Counters REI-P Error Counter (high byte) for Path 2 R Counters Tandem Conn. Error Counter (low byte) Mindspeed Technologies CX29610 CX29610 Data Sheet Page Description Number page 4-25 page 4-23 page 4-40 page 4-32 page 4-51 ...
Page 117
... CX29610 CX29610 Data Sheet Table 4-2. Processor Memory Map (8 of 12) Address Port 1 Port 2 Port 3 Port 4 0x0E5 0x2E5 0x4E5 0x6E5 TCCNTH-2 0x0E6 0x2E6 0x4E6 0x6E6 0x0E7 0x2E7 0x4E7 0x6E7 NDFCNT-2 0x0E8 0x2E8 0x4E8 0x6E8 PJCNTL-2 0x0E9 0x2E9 0x4E9 0x6E9 PJCNTH-2 0x0EA 0x2EA 0x4EA ...
Page 118
... Counters BIP Error Counter (low byte) for Path 3 R Counters BIP Error Counter (high byte) for Path 3 R Counters REI-P Error Counter (low byte) for Path 3 R Counters REI-P Error Counter (high byte) for Path 3 Mindspeed Technologies CX29610 CX29610 Data Sheet Page Description Number page 4-25 page 4-23 page 4-40 page 4-32 page 4-51 ...
Page 119
... CX29610 CX29610 Data Sheet Table 4-2. Processor Memory Map (10 of 12) Address Port 1 Port 2 Port 3 Port 4 0x124 0x324 0x524 0x724 TCCNTL-3 0x125 0x325 0x525 0x725 TCCNTH-3 0x126 0x326 0x526 0x726 0x127 0x327 0x527 0x727 NDFCNT-3 0x128 0x328 0x528 0x728 PJCNTL-3 0x129 0x329 0x529 ...
Page 120
... Receive F3 Overhead Status Register for Path 4 RXK3-4 R — Receive K3 Overhead Status Register for Path 4 RXN1-4 R — Receive N1 Overhead Status Register for Path 4 Mindspeed Technologies CX29610 CX29610 Data Sheet Page Description Number page 4-61 page 4-61 page 4-63 page 4-64 page 4-25 page 4-23 page 4-40 page 4-32 page 4-51 page 4-50 ...
Page 121
... CX29610 CX29610 Data Sheet Table 4-2. Processor Memory Map (12 of 12) Address Port 1 Port 2 Port 3 Port 4 0x15D 0x35D 0x55D 0x75D 0x15E 0x35E 0x55E 0x75E 0x15F 0x35F 0x55F 0x75F 0x160 0x360 0x560 0x760 B3CNTL-4 0x161 0x361 0x561 0x761 B3CNTH-4 0x162 0x362 0x562 0x762 RPCNTL-4 ...
Page 122
... Name SFThresh[3:0] Threshold exponent value for setting signal failed status—default - SDThresh[3:0] Threshold exponent value for setting signal degraded -6 status—default is 10 Mindspeed Technologies ™ CX29610 CX29610 Data Sheet Port 3 Port 4 0x43E 0x63E Description Port 3 Port 4 0x41E 0x61E Description . 29610-DSH-001-C ...
Page 123
... CX29610 CX29610 Data Sheet B1CNTH (Section BIP Error Counter [High Byte]) hex address: The B1CNTH counter tracks the number of Section BIP errors. Bit Default 7-0 xxh B1CNTL (Section BIP Error Counter [Low Byte]) hex address: The B1CNTL counter tracks the number of Section BIP errors. ...
Page 124
... Path 1 0x0E1 0x2E1 Path 2 0x121 0x321 Path 3 0x161 0x361 Path 4 Name B3Cnt[15:8] Path BIP error counter high byte Mindspeed Technologies ™ CX29610 CX29610 Data Sheet Port 3 Port 4 0x450 0x650 Description Port 3 Port 4 0x451 0x651 Description Port 3 Port 4 0x4A1 0x6A1 0x4E1 0x6E1 ...
Page 125
... CX29610 CX29610 Data Sheet B3CNTL (Path BIP Error Counter [Low Byte]) hex address: The B3CNTL counter tracks the number of Path BIP errors. a payload defect. Bit Default 7-0 xxh BUSMODE (SI-Bus Mode Control Register) The BUSMODE register controls the operating mode of the SI-Bus. Must be set to 0xAA for proper operation ...
Page 126
... NELnLoop When written to 1, Near End Line Loopback is enabled. This loopback connects the line-side receive PECL clock/data inputs to the line-side transmit PECL clock/data outputs. Mindspeed Technologies ™ CX29610 CX29610 Data Sheet Port 3 Port 4 0x414 0x614 Description 29610-DSH-001-C ...
Page 127
... CX29610 CX29610 Data Sheet CLKRECPD (Clock Recovery/Power Down Control Register) hex address: The CLKRECPD register controls the CDR powerdown logic and VCO clock select. Bit Default 29610-DSH-001-C Port 1 Port 2 0x013 0x213 Name VcoTstClk_sel VCO test clock select 0— ...
Page 128
... When written to 0, status registers are updated continuously. EnCntrLat When written to 1, one-second latching is enabled for all error counters. When written to 0, error count information is updated continuously. — Reserved, set to zero. Mindspeed Technologies ™ CX29610 CX29610 Data Sheet Port 4 0x610 Description 29610-DSH-001-C ...
Page 129
... CX29610 CX29610 Data Sheet DOWNALM (Downstream Alarm Control Register) hex address: The DOWNALM register controls the downstream AIS options, receive scrambler disable, and receive pointer replication. Bit Default 7 1 AutoDownAIS AutoDownAIS- AutoDownAIS- AutoDownAIS- AutoDownAIS-P4 ...
Page 130
... EnS1Intr This bit enables the S1 byte change interrupt. EnS1_UnstableIntr This bit enables the S1_Unstable byte change interrupt. EnZ1Z2Intr This bit enables the byte change interrupt. Mindspeed Technologies ™ CX29610 CX29610 Data Sheet Port 3 Port 4 0x43A 0x63A Description Port 3 Port 4 0x439 ...
Page 131
... CX29610 CX29610 Data Sheet ENPNTR (Pointer Interrupt Mask Control Register) hex address: The ENPNTR register controls the pointer interrupt enables. Bit Default 29610-DSH-001-C Port 1 Port 2 0x08D 0x28D Path 1 0x0CD 0x2CD Path 2 0x10D 0x30D ...
Page 132
... EnPath4Intr This bit is a global enable for SONET Path/Pointer 4 interrupt sources in this port when set to 1. EnSIParIntr This bit enables the SI-Bus parity error interrupt. Mindspeed Technologies ™ CX29610 CX29610 Data Sheet Port 3 Port 4 0x418 0x618 Description 29610-DSH-001-C ...
Page 133
... CX29610 CX29610 Data Sheet ENPTH (Receive Path Interrupt Mask Control Register) hex address: The ENPTH register controls receive path interrupt enables. Bit Default 29610-DSH-001-C Port 1 Port 2 0x08C 0x28C Path 1 0x0CC 0x2CC Path 2 0x10C ...
Page 134
... This bit is a global enable for Port3 interrupt sources when set to 1. EnPort2Int This bit is a global enable for Port2 interrupt sources when set to 1. EnPort1Int This bit is a global enable for Port1 interrupt sources when set to 1. Mindspeed Technologies ™ CX29610 CX29610 Data Sheet Port 3 Port 4 0x438 0x638 Description Description 29610-DSH-001-C ...
Page 135
... CX29610 CX29610 Data Sheet ERRINS (Error Insertion Control Register) hex address: The ERRINS register controls error insertion into various octets for diagnostic purposes. These bits are automatically cleared by internal circuitry after the indicated error insertion has taken place. Clearing takes precedence over a simultaneous write operation to this register. ...
Page 136
... MasterReset When written to 1, all internal state machines are held in reset mode AND all control registers are set to their default values (except bit 0 in this register). Mindspeed Technologies ™ CX29610 CX29610 Data Sheet Description 1 29610-DSH-001-C ...
Page 137
... CX29610 CX29610 Data Sheet LININT (Receive Line Interrupt Indication Status Register) hex address: The LININT register indicates that a change of status has occurred within its affiliated status signals. Bit Default NOTE(S): (1) Single event interrupt—only a positive transition on the corresponding status bit causes this interrupt to occur. Reading the interrupt register clears the interrupt ...
Page 138
... Path 1 0x0EA 0x2EA Path 2 0x12A 0x32A Path 3 0x16A 0x36A Path 4 Name NJCnt[7:0] Negative pointer justification counter low byte Mindspeed Technologies ™ CX29610 CX29610 Data Sheet Port 3 Port 4 0x4AB 0x6AB 0x4EB 0x6EB 0x52B 0x72B 0x56B 0x76B Description Port 3 Port 4 0x4AA 0x6AA 0x4EA ...
Page 139
... CX29610 CX29610 Data Sheet PJCNTH (Positive Pointer Justification Counter [High Byte]) hex address: The PJCNTH counter controls the high bits of the 11-bit Positive Pointer Justification Counter. Bit Default 7-3 — 2-0 xxh PJCNTL (Positive Pointer Justification Counter [Low Byte]) hex address: The PJCNTL counter controls the low bits of the 11-bit Positive Pointer Justification Counter. ...
Page 140
... This bit indicates that an F3 byte change interrupt has occurred. F3Int This bit indicates that a K3 byte change interrupt has occurred. 1 K3Int 2 This bit indicates that an ISF interrupt has occurred. ISFInt Mindspeed Technologies ™ CX29610 CX29610 Data Sheet Port 3 Port 4 0x491 0x691 0x4D1 0x6D1 0x511 0x711 0x551 0x751 ...
Page 141
... CX29610 CX29610 Data Sheet PNTRSTAT (Receive H1/H2 Pointer Action Status Register) hex address: The PNTRSTAT register reports that the corresponding path event has occurred or is active. Bit Default 3-2 xx 1-0 xx NOTE(S): (1) This status shows an event that has occurred since the register was last read. ...
Page 142
... This bit indicates that a Path/Pointer 3 interrupt has occurred in this port. Path4Intr This bit indicates that a Path/Pointer 4 interrupt has occurred in this port. SIParIntr This bit indicates that a parity error occurred on the receive SI-Bus interface for this port. Mindspeed Technologies ™ CX29610 CX29610 Data Sheet Port 4 0x419 0x619 Description 29610-DSH-001-C ...
Page 143
... CX29610 CX29610 Data Sheet PORTMAP (Port Mapping Control Register) hex address: 0x001 The PORTMAP register controls the SI-Bus cross-connect mappings. These controls connect the respective SONET line side ports to the desired SI-Bus ports. Note that only one SONET port should be connected to each SI-Bus port for reliable operation ...
Page 144
... Port 1 Port 2 Port 3 0x017 0x217 0x417 Name Reserved, set to zero. EnTxPrbs Enable the PRBS generator in the Transmit SONET/SDH framer. EnRxPrbs Enable the PRBS checker in the Receive SONET/SDH framer. Mindspeed Technologies ™ CX29610 CX29610 Data Sheet Port 4 0x617 Description 29610-DSH-001-C ...
Page 145
... CX29610 CX29610 Data Sheet PROVC2 (Provisioned C2 Control Register) hex address: The PROVC2 register sets the provisioned C2 value. Bit Default 7-0 01h 29610-DSH-001-C Port 1 Port 2 0x084 0x284 Path 1 0x0C4 0x2C4 Path 2 0x104 0x304 Path 3 0x144 0x344 Path 4 Name ProvC2[1:8] Provisioned value for C2. This is the value compared to the received C2 value to determine PLM-P and UNEQ-P alarms ...
Page 146
... When written to 1, this bit causes the contents of ERRPAT bits 7–4 InsREI transmitted as the REI-P value in the G1 byte for one transmit frame. — Reserved, set to zero. Mindspeed Technologies ™ CX29610 CX29610 Data Sheet Port 3 Port 4 0x483 0x683 0x4C3 0x6C3 0x503 0x703 ...
Page 147
... When written to 0, the G1 byte is generated in the CX29610. When written to 1, the G1 byte is accepted from the SI-Bus. InsF2 When written to 0, the F2 byte is generated in the CX29610. When written to 1, the F2 byte is accepted from the SI-Bus. InsH4 When written to 0, the H4 byte is generated in the CX29610. When written to 1, the H4 byte is accepted from the SI-Bus ...
Page 148
... This bit indicates that a PLM-P interrupt has occurred. PLM-Pint This bit indicates that an Uneq-P interrupt has occurred. 2 Uneq-Pint 1 This bit indicates that a Path Trace interrupt has occurred. PthTraceInt Mindspeed Technologies ™ CX29610 CX29610 Data Sheet Port 3 Port 4 0x490 0x690 0x4D0 0x6D0 0x510 0x710 0x550 0x750 ...
Page 149
... CX29610 CX29610 Data Sheet PWRDWN (PowerDown/Three-State Control Register) The PWRDWN register controls the powerdown of ports and SI-Bus three-stating. hex address: 0x003 Bit Default RLCNTH (REI-L Error Counter [High Byte]) hex address: High byte of the Line REI error counter. ...
Page 150
... Port 1 Port 2 0x055 0x255 Name RLCnt[15:8] REI-L error counter mid byte. Port 1 Port 2 0x054 0x254 Name RLCnt[7:0] REI-L error counter low byte. Mindspeed Technologies ™ CX29610 CX29610 Data Sheet Port 3 Port 4 0x455 0x655 Description Port 3 Port 4 0x454 0x654 Description 29610-DSH-001-C ...
Page 151
... CX29610 CX29610 Data Sheet RPCNTH (REI-P Error Counter [High Byte]) hex address: High byte of the Path REI error counter. Bit Default 7-0 xxh RPCNTL (REI-P Error Counter [Low Byte]) hex address: Low byte of the Path REI error counter. Bit Default 7-0 xxh 29610-DSH-001-C ...
Page 152
... Path 1 0x0D8 0x2D8 Path 2 0x118 0x318 Path 3 0x158 0x358 Path 4 Name RxC2[1:8] Receive value for the C2 Path Overhead byte. Mindspeed Technologies ™ CX29610 CX29610 Data Sheet Port 3 Port 4 0x44A 0x64A Description Port 3 Port 4 0x498 0x698 0x4D8 0x6D8 0x518 0x718 0x558 0x758 ...
Page 153
... CX29610 CX29610 Data Sheet RXF1 (Receive F1 Section Overhead Status Register) hex address: The RXF1 register contains the received F1 Section Overhead byte. An F1INT in the SECINT is reported when this byte changes, if enabled. No integration is performed on this byte, so any change in the received by is reflected here. ...
Page 154
... Port 2 0x09A 0x29A Path 1 0x0DA 0x2DA Path 2 0x11A 0x31A Path 3 0x15A 0x35A Path 4 Name RxF3[1:8] Receive value for the Z3/F3 Path Overhead byte. Mindspeed Technologies ™ CX29610 CX29610 Data Sheet Port 3 Port 4 0x49A 0x69A 0x4DA 0x6DA 0x51A 0x71A 0x55A 0x75A Description 29610-DSH-001-C ...
Page 155
... CX29610 CX29610 Data Sheet RXFRMREF (Receive Frame Reference Control Register) hex address: The RXFRMREF register controls the receive rx8khz_n clock outputs. Bit Default 7 0 RXFRMLOL_DIS 6 0 RXFRMLOS_DIS 5 0 RXFRMSEF_DIS 4 0 RXFRMLOF_DIS 3 0 RXFRMAISL_DIS 2 0 RXFRMREF_DIS 1-0 00 RXFRMREF_SEL[1:0] RXK1 (Receive K1 Line Overhead Status Register) hex address: The RXK1 register contains the received K1 Line Overhead byte ...
Page 156
... Path 1 0x0DB 0x2DB Path 2 0x11B 0x31B Path 3 0x15B 0x35B Path 4 Name RxK3[1:8] Receive value for the Z4/K3 Path Overhead byte. Mindspeed Technologies ™ CX29610 CX29610 Data Sheet Port 4 0x62F Description Port 3 Port 4 0x49B 0x69B 0x4DB 0x6DB 0x51B 0x71B 0x55B 0x75B Description 29610-DSH-001-C ...
Page 157
... CX29610 CX29610 Data Sheet RXLIN (Receive Line Overhead Status Register) hex address: The RXLIN register contains status information for the receive Line Overhead. Bit Default NOTE(S): (1) This status shows an event that has occurred since the register was last read. ...
Page 158
... Path 1 0x0D5 0x2D5 Path 2 0x115 0x315 Path 3 0x155 0x355 Path 4 Name 1 Receive value for the H2 Line Overhead pointer byte. RxPntr[7:0] Mindspeed Technologies ™ CX29610 CX29610 Data Sheet Port 3 Port 4 0x495 0x695 0x4D5 0x6D5 0x515 0x715 0x555 0x755 Description 29610-DSH-001-C ...
Page 159
... CX29610 CX29610 Data Sheet RXPTH (Receive Path Overhead Status Register) hex address: The RXPTH register contains status information for the receiver Path Overhead. Bit Default NOTE(S): (1) This status shows an event that has occurred since the register was last read. ...
Page 160
... Path 4 Name — Reserved, set to zero. RxG1[5,6,7] Receive value for G1 byte bits 5,6,7 in the path overhead. — Reserved, set to zero. Mindspeed Technologies ™ CX29610 CX29610 Data Sheet Port 3 Port 4 0x4B0 0x6B0 0x4F0 0x6F0 0x530 0x730 0x570 0x770 Description Port 3 Port 4 ...
Page 161
... CX29610 CX29610 Data Sheet RXS1 (Receive S1 Line Overhead Status Register) hex address: The RXS1 register contains the received S1 Line Overhead byte. This byte is allocated for transporting synchronization status messages. This byte is defined only for the first STS-1 of the STS-3/STS-12 signal. ...
Page 162
... Name RxZ1b[1:8] Receive value for the first Z1 overhead byte. Port 1 Port 2 0x032 0x232 Name RxZ1c[1:8] Receive value for the second Z1 overhead byte. Mindspeed Technologies ™ CX29610 CX29610 Data Sheet Port 3 Port 4 0x45C 0x65C Description Port 3 Port 4 0x431 0x631 Description Port 3 Port 4 ...
Page 163
... CX29610 CX29610 Data Sheet RXZ2a (Receive Z2a Overhead Status Register) hex address: The RXZ2a register contains the first received Z2 octet. Bit Default 7-0 xxh RXZ2b (Receive Z2b Overhead Status Register) hex address: The RXZ2b register contains the second received Z2 octet. Bit Default ...
Page 164
... This bit indicates that a Section Trace interrupt has occurred. SecTraceInt 1 This bit indicates that an F1 byte change interrupt has occurred. F1Int Port 1 Port 2 0x048 0x248 Name SEFCnt[7:0] Out of frame event counter. Mindspeed Technologies ™ CX29610 CX29610 Data Sheet Port 3 Port 4 0x43C 0x63C Description Port 3 Port 4 0x448 0x648 Description 29610-DSH-001-C ...
Page 165
... CX29610 CX29610 Data Sheet STATUS (Status Output Control Register) hex address: The STATUS register controls the functionality of the StatOut pins. Bit Default 5-4 00 3-2 00 1-0 00 29610-DSH-001-C Port 1 Port 2 0x011 0x211 Name — Reserved, set to zero. StatPinMode When written to 0, the StatOut[1:0] pins for this port reflect the internal status selected in bits 5– ...
Page 166
... Bypasses the SONET transmission/reception used to debug and test the CDR block. Line DCC internal reception-to-transmission loopback. Section DCC internal reception-to-transmission loopback. E1 and E2 orderwire internal transmission-to-reception loopback. — Reserved Mindspeed Technologies ™ CX29610 CX29610 Data Sheet Description Description 29610-DSH-001-C ...
Page 167
... CX29610 CX29610 Data Sheet TCCNTH (Tandem Connection Error Counter [High Byte]) hex address: The TCCNTH counter counts tandem connection errors. Bit Default 7-0 xxh TCCNTL (Tandem Connection Error Counter [Low Byte]) hex address: The TCCNTL counter counts tandem connection errors. Bit Default ...
Page 168
... TxC2[1:8] Transmit value for C2 overhead byte. Port 1 Port 2 Port 3 0x024 0x224 0x424 Name TxF1[1:8] Transmit value for F1 section overhead byte. Mindspeed Technologies ™ CX29610 CX29610 Data Sheet Port 3 Port 4 0x485 0x685 0x4C5 0x6C5 0x505 0x705 0x545 0x745 Description Port 4 0x624 Description ...
Page 169
... CX29610 CX29610 Data Sheet TXF2 (Transmit F2 Path Overhead Control Register) hex address: The TXF2 register holds the value of the F2 path overhead byte that is inserted into the transmit frame. Insertion of the F2 path overhead byte is controlled by the PTHINSL control register bit 3. Bit Default ...
Page 170
... Port 1 Port 2 Port 3 0x025 0x225 0x425 Name TxK1[1:8] Transmit value for K1 overhead byte. Port 1 Port 2 Port 3 0x026 0x226 0x426 Name TxK2[1:8] Transmit value for K2 overhead byte. Mindspeed Technologies ™ CX29610 CX29610 Data Sheet Port 4 0x625 Description Port 4 0x626 Description 29610-DSH-001-C ...
Page 171
... CX29610 CX29610 Data Sheet TXK3 (Transmit K3 Overhead Control Register) hex address: The TXK3 register controls the insertion of the K3 Path overhead byte position in the transmitter if enabled by setting PTHINSL bit 0 low. Bit Default 7-0 00h TXLIN (Transmit Line Overhead Control Register) hex address: The TXLIN register controls the transmission of various octets in the Line Overhead of the SONET frame. ...
Page 172
... Port 1 Port 2 0x089 0x289 Path 1 0x0C9 0x2C9 Path 2 0x109 0x309 Path 3 0x149 0x349 Path 4 Name TxN1[1:8] Transmit value for N1 overhead byte. Mindspeed Technologies ™ CX29610 CX29610 Data Sheet Port 3 Port 4 0x469 0x669 0x4C9 0x6C9 0x509 0x709 0x549 0x749 Description 29610-DSH-001-C ...
Page 173
... CX29610 CX29610 Data Sheet TXPNTR (Transmit H1/H2/H3 Pointer Control Register) hex address: The TXPNTR register controls the pointer value for the transmitted SPE. SONET STS-3 modes will have three SPEs, represented by path registers 1-3. The SONET OC-12 and SDH STM-4 AU-3 modes will use one physical line port (port 1) but have twelve SPEs ...
Page 174
... When written to 1, path RDI is automatically generated for at least 20 frames upon reception of LOS, LOF, LOP, AIS-L, AIS-P, UNEQ-P, or PLM-P. When written to 0, path RDI is inserted from bits 3–1 of this register. Mindspeed Technologies ™ CX29610 CX29610 Data Sheet Port 3 Port 4 0x481 0x681 0x4C1 0x6C1 ...
Page 175
... CX29610 CX29610 Data Sheet TXPTHBUF (Transmit Path Trace Circular Buffer) hex address: The TXPTHBUF buffer, the J1 byte, is used to repeatedly transmit a 64-byte, fixed-length string so a receiving terminal in a path can verify its continued connection to the intended transmitter. The 64-byte J1 transmit buffers are implemented with a 16-bit wide internal buffer, therefore two writes to the TXPTHBUF register must be executed before the entire 16-bits is written to the internal buffer ...
Page 176
... When written to 1, the E1 byte is generated from data shifted in the TxE1 input pin. When written to 0, the E1 byte contains 00h. Port 1 Port 2 0x058 0x258 Name TxSecBuf[7:0] Transmit section trace circular buffer. Mindspeed Technologies ™ CX29610 CX29610 Data Sheet Port 3 Port 4 0x41C 0x61C Description Port 3 Port 4 0x458 0x658 Description 29610-DSH-001-C ...
Page 177
... CX29610 CX29610 Data Sheet TXZ1b (Transmit Z1b Overhead Control Register) hex address: The TXZ1b register controls the insertion of the Z1 Line overhead byte position in the transmitter. Z1b is Z1-2 in STS-3 mode and Z1-5 through Z1-8 in STS-12 mode, presented in registers for ports 1–4, respectively. Bit Default ...
Page 178
... Part[3:0] This is the part number that uniquely identifies the CX29610. Ver[3:0] This is the version number that uniquely identifies the specific version of the CX29610. Version numbers start at 1 for the first version and are incremented for each revision thereafter. Mindspeed Technologies ™ ...
Page 179
... CX29610 CX29610 Data Sheet WINDOW_H (CDR Window Register [high byte]) hex address: 0x009 The WINDOW_H register control PLL lock and capture window settings of the CDR. Bit Default 7–0 0x03 WINDOW_L (CDR Window Register [low byte]) hex address: 0x008 The WINDOW_L register control PLL lock and capture window settings of the CDR. ...
Page 180
... The value is not written until after the WINHYST2_H register value is written. 4-72 Name — Reserved. — The second hysteresis value to CDR PLL block, high byte. Name — The second hysteresis value to the CDR PLL block, low byte. Mindspeed Technologies ™ CX29610 CX29610 Data Sheet Description Description 1 29610-DSH-001-C ...
Page 181
... CX29610 CX29610 Data Sheet 4.2 Register Differences between STS-3 and STS-12 Modes The preceding register map details the registers for 4xSTS-3 mode. Some registers take on different functionality in STS-12 mode than in STS-3 mode. STS-3 numbering remains the same in either mode as shown in Figure 1-4 and Figure 1-5 ...
Page 182
... Registers 4.2 Register Differences between STS-3 and STS-12 Modes 4-74 Mindspeed Technologies ™ CX29610 CX29610 Data Sheet 29610-DSH-001-C ...
Page 183
... Electrical and Mechanical This chapter describes the electrical and mechanical aspects of the CX29610. Included are timing diagrams, absolute maximum ratings, DC characteristics, and mechanical drawings. 5.1 Timing Specifications This section provides timing diagrams and descriptions for the various interfaces of the CX29610. that appear in the timing diagrams. The timing relationship labels are numbered when they occur more than once in a diagram so that each label is unique ...
Page 184
... Pulse Width Low pwl t Setup Time s t Setup High Time sh t Setup Low Time sl t Hold Time h t Hold High Time hh 5-2 Input Input Input Data Clock Data Clock Data Clock Clock Data Clock Data Mindspeed Technologies ™ CX29610 CX29610 Data Sheet Waveform 29610-DSH-001-C ...
Page 185
... CX29610 CX29610 Data Sheet Table 5-1. Timing Diagram Nomenclature ( Symbol Timing Relationship t Hold Low Time hl t Propagation Delay pd t Propagation Delay - High-to-Low pdhl t Propagation Delay - Low-to-High pdlh t Enable Time en t Enable Time - High-impedance to Low enzl Enable 29610-DSH-001-C 5.0 Electrical and Mechanical Specifications ...
Page 186
... Recovery Time rec t Period per Figure 5-1 illustrates how output waveforms are defined. 5-4 Input Output Input Output Input Output Input Output Async. Input Clock Input illustrates how input waveforms are defined and Mindspeed Technologies ™ CX29610 CX29610 Data Sheet Waveform Figure 5-2 29610-DSH-001-C ...
Page 187
... CX29610 CX29610 Data Sheet Figure 5-1. Input Waveform Figure 5-2. Output Waveform 29610-DSH-001-C 5.0 Electrical and Mechanical Specifications t t rise fall t per t t rise fall t pwh t per Mindspeed Technologies ™ 5.1 Timing Specifications 2.0 V 1.5 V 0.8 V 100518_025 2.4 V 1 pwl 100518_026 5-5 ...
Page 188
... T T asu ahd T T tssu tshd T cssu T rwsu T enzl Min 7 Mindspeed Technologies ™ CX29610 CX29610 Data Sheet T T tad tad T cshd T rwhd T adv adz T T add adh T dislz 100518_027 Max Unit Load 56 ns — — ...
Page 189
... CX29610 CX29610 Data Sheet Table 5-2. MPC 860 Read Timing Table Label Description T Chip Select setup to clock rise cssu T Chip Select hold to clock rise cshd T Read/Write setup to clock rise rwsu T Read/Write hold to clock rise rwhd T Data bus driven from clock rise add ...
Page 190
... T asu T T tssu tshd T tad T cssu T rwsu T adsu Min Mindspeed Technologies ™ CX29610 CX29610 Data Sheet T ahd T tad T cshd T rwhd T adhd 100518_028 Max Unit Load — ns — — ns — — ns — — ns — — ...
Page 191
... CX29610 CX29610 Data Sheet 5.1.1.2 Mindspeed EBUS Interface Figure 5-5. EBUS Read Timing Diagram MClk Tasu Tahd MAD Address[7:0] Tasu Tahd MA Address[10:8] Tcssu MCS* Ttshd Ttssu MTS* (ALE) MRD* Tenzl MIntr* NOTE: The chip select signal (MCS*) needs to go inactive for at least one cycle Table 5-4 ...
Page 192
... T Enable, MIntr* from the rising edge of MClk enzl T Disable, MIntr* from the rising edge of MClk dislz 5-10 Min Mindspeed Technologies ™ CX29610 CX29610 Data Sheet Max Unit Load — ns — ...
Page 193
... CX29610 CX29610 Data Sheet Figure 5-6. EBUS Write Timing Diagram MClk Tasu Tahd MAD Address[7:0] Tasu Tahd MA Address[10:8] Tcssu MCS* Ttshd Ttssu MTS* (ALE) MRW* (high) MRD* NOTE: The chip select signal (MCS*) needs to go inactive for at least one cycle Table 5-5. EBUS Write Timing Table ...
Page 194
... Electrical and Mechanical Specifications 5.1 Timing Specifications 5.1.2 SI-Bus Transmit Timing The CX29610 generates clock and control signals and the slave devices respond with data/parity. The CX29610 generates control outputs synchronously with the rising edge of STxClk_n and samples returning data on the rising edge of TxClk. ...
Page 195
... CX29610 CX29610 Data Sheet 5.1.3 SI-Bus Receive Timing The CX29610 generates clock, data, and control signals. The CX29610 generates control and data outputs synchronously with the rising edge of RxClk. The nominal clock frequency is 19.44 MHz but will be gapped in various modes. Gapping blanks out high pulses. ...
Page 196
... VALID VALID T T pwh Min — — 2.5 100 Mindspeed Technologies ™ CX29610 CX29610 Data Sheet T dis VALID pwl 100518_045 Max Unit Load — ns — — ns — — ns — — ns — — ns — — ns — — ...
Page 197
... CX29610 CX29610 Data Sheet 5.1.5 One-second Interface Timing Figure 5-10 the One-second interface. Figure 5-10. One-second Timing Diagram Ref8kHzClk OneSecOut OneSecIn PLLRefClk Table 5-9. One-second Timing Table Symbol Description T Period, Ref8kHzClk per1 T Pulse Width High, Ref8kHzClk pwh1 T Pulse Width Low, Ref8kHzClk pwl1 T Propagation Delay, OneSecOut from the rising ...
Page 198
... Min Typical — 1.74 0.520 — 1.10 — 50 — 25 — 50 — 25 — Mindspeed Technologies ™ CX29610 CX29610 Data Sheet pwl 100518_047 Max Unit Load µs — µs — µs — — — — ns — — ...
Page 199
... CX29610 CX29610 Data Sheet Table 5-11. SDCC Timing Table Symbol Description T Period, RxSDCC_Clk_n/TxSDCC_Clk_n per T Pulse Width High, RxSDCC_Clk_n/ pwh TxSDCC_Clk_n T Pulse Width Low, RxSDCC_Clk_n/ pwl TxSDCC_Clk_n T Setup, RxSDCC_Dat_n to the rising edge s1 of RxSDCC_Clk_n T Hold, RxSDCC_Dat_n from the rising h1 edge of RxSDCC_Clk_n T Setup, TxSDCC_Dat_n to the rising edge ...
Page 200
... Pulse Width High pwh T Pulse Width Low pwl 5-18 and Table 5-12 illustrate the timing requirements and characteristics T per T T pwh Min Typical — 51.44 23 — 23 — Mindspeed Technologies ™ CX29610 CX29610 Data Sheet pwl 100518_048 Max Unit Load — ns — — — 29610-DSH-001-C ...