A43L1632V-6 AMICC [AMIC Technology], A43L1632V-6 Datasheet - Page 11

• Manufacturer Part Number: A43L1632V-6
• Description: 512K X 32 Bit X 4 Banks Synchronous DRAM
• Manufacturer: AMICC [AMIC Technology]

Simplified Truth Table
Register
Refresh
Bank Active & Row Addr.
Read &
Column Addr. Auto Precharge Enable
Write &
Column Addr. Auto Precharge Enable
Burst Stop
Precharge
Clock Suspend or
Active Power Down
Precharge Power Down Mode
DQM
No Operation Command
Deep Power Down Entry
Deep Power Down Exit
Note : 1. OP Code: Operand Code
PRELIMINARY
2. MRS can be issued only when all banks are at precharge state.
3. Auto refresh functions is same as CBR refresh of DRAM.
4. BS0, BS1 : Bank select address.
5. During burst read or write with auto precharge, new read/write command cannot be issued.
6. DQM sampled at positive going edge of a CLK masks the data-in at the very CLK (Write DQM latency is 0)
7. After Deep Power Down mode exit, a full new initialization of the memory device is mandatory.
A0~A10, BS0, BS1: Program keys. (@MRS)
A new command can be issued after 2 clock cycle of MRS.
The automatical precharge without Row precharge command is meant by “Auto”.
Auto/Self refresh can be issued only when all banks are at precharge state.
If both BS1 and BS0 are “Low” at read, write, row active and precharge, bank A is selected.
If both BS1 is “Low” and BS0 is “High” at read, write, row active and precharge, bank B is selected.
If both BS1 is “High” and BS0 is “Low” at read, write, row active and precharge, bank C is selected.
If both BS1 and BS0 are “High” at read, write, row active and precharge, bank D is selected.
If A10/AP is “High” at row precharge, BS1 and BS0 is ignored and all banks are selected.
Another bank read/write command can be issued at every burst length.
but masks the data-out Hi-Z state after 2 CLK cycles. (Read DQM latency is 2)
Mode Register Set
Auto Refresh
Self
Refresh
Auto Precharge Disable
Auto Precharge Disable
Bank Selection
Both Banks
Command
(December, 2004, Version 0.0)
Entry
Exit
Entry
Entry
Exit
Exit
CKEn-1 CKEn
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
H
H
H
H
H
X
X
X
X
X
X
X
L
L
L
L
CS
10
H
H
X
H
H
H
X
L
L
L
L
L
L
L
L
L
L
L
L
L
(V = Valid, X = Don’t Care, H = Logic High, L = Logic Low)
RAS CAS
H
X
H
H
H
H
X
X
H
X
V
X
H
X
H
X
L
L
L
L
X
H
H
H
X
H
H
H
X
X
H
X
V
X
H
X
X
L
L
L
L
WE
H
H
X
H
H
H
X
X
H
X
V
X
H
X
X
L
L
L
L
L
DQM BS0
X
X
X
X
X
X
X
X
X
X
X
X
V
X
X
X
AMIC Technology, Corp.
BS1
V
V
V
V
X
OP CODE
A10
/AP
H
H
H
L
L
L
Row Addr.
X
X
X
X
X
X
X
X
X
A9~A0,
Column
Column
Addr.
Addr.
X
A43L1632
Notes
1,2
4,5
4,5
3
3
3
3
4
4
4
6
7