A43L1632V-6 AMICC [AMIC Technology], A43L1632V-6 Datasheet - Page 29

• Manufacturer Part Number: A43L1632V-6
• Description: 512K X 32 Bit X 4 Banks Synchronous DRAM
• Manufacturer: AMICC [AMIC Technology]

Page Read Cycle at Different Bank @Burst Length = 4
PRELIMINARY
CLOCK
A10/AP
ADDR
(CL=2)
(CL=3)
CKE
RAS
CAS
BS0
DQM
DQ
DQ
BS1
CS
WE
* Note : 1.
*Note 1
0
Row Active
(A-Bank)
RAa
RAa
1
2. To interrupt a burst read by row precharge, both the read and the precharge banks must be the same.
(December, 2004, Version 0.0)
CS
2
Row Active
can be don’t care when
(B-Bank)
RBb
RBb
3
(A-Bank)
Read
CAa
4
5
Row Active
(C-Bank)
QAa0 QAa1 QAa2
RCc
RCc
6
RAS
(B-Bank)
QAa0 QAa1 QAa2
Read
CBb
7
,
Precharge
(A-Bank)
CAS
8
Row Active
(D-Bank)
and
QBb0
RDd
RDd
9
28
WE
(C-Bank)
High
QBb0
Read
QBb1
CCc
10
are high at the clock high going edge.
Precharge
(B-Bank)
QBb2
QBb1
11
QCc0 QCc1 QCc2 QDd0 QDd1 QDd2
QBb2
12
(D-Bank)
QCc0 QCc1 QCc2 QDd0 QDd1 QDd2
Read
CDd
13
Precharge
(C-Bank)
14
AMIC Technology, Corp.
15
Precharge
(D-Bank)
16
*Note 2
17
: Don't care
A43L1632
18
19