A43L1632V-6 AMICC [AMIC Technology], A43L1632V-6 Datasheet - Page 28
A43L1632V-6
Manufacturer Part Number
A43L1632V-6
Description
512K X 32 Bit X 4 Banks Synchronous DRAM
Manufacturer
AMICC [AMIC Technology]
Datasheet
1.A43L1632V-6.pdf
(43 pages)
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PRELIMINARY
Page Read & Write Cycle at Same Bank @Burst Length=4
CLOCK
A10/AP
ADDR
(CL=2)
(CL=3)
CKE
RAS
CAS
BS0
BS1
DQM
CS
DQ
DQ
WE
*Note : 1. To write data before burst read ends, DQM should be asserted three cycle prior to write
0
Row Active
(A-Bank)
Ra
Ra
2. Row precharge will interrupt writing. Last data input, t
3. DQM should mask invalid input data on precharge command cycle when asserting precharge
1
command to avoid bus contention.
before end of burst. Input data after Row precharge cycle will be masked internally.
(December, 2004, Version 0.0)
2
t
RCD
3
(A-Bank)
Read
Ca
4
5
(A-Bank)
Read
Qa0
Cb
6
Qa1
Qa0
7
Qb0
Qa1
8
Qb0
Qb1
9
27
High
*Note1
RDL
Qb2
Qb1
10
before Row precharge, will be written.
11
(A-Bank)
Write
Dc0
Dc0
Cc
12
Dc1
Dc1
13
t
CDL
(A-Bank)
Write
Dd0
Dd0
Cd
14
Dd1
Dd1
AMIC Technology, Corp.
15
*Note3
t
*Note 2
RDL
16
Precharge
(A-Bank)
17
: Don't care
18
A43L1632
19
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