A43L1632V-6 AMICC [AMIC Technology], A43L1632V-6 Datasheet - Page 16

• Manufacturer Part Number: A43L1632V-6
• Description: 512K X 32 Bit X 4 Banks Synchronous DRAM
• Manufacturer: AMICC [AMIC Technology]

All Banks Precharge
All banks can be precharged at the same time by using
Precharge all command. Asserting low on
t
the end of tRP after performing precharge all, all banks are in
idle state.
Auto Refresh
The storage cells of SDRAM need to be refreshed every
64ms to maintain data. An auto refresh cycle accomplishes
refresh of a single row of storage cells. The internal counter
increments automatically on every auto refresh cycle to
refresh all the rows. An auto refresh command is issued by
asserting low on
all banks being in idle state and the device is not in power
down mode (CKE is high in the previous cycle). The time
required to complete the auto refresh operation is specified
by “t
can be calculated by dividing “t
then rounding up to the next higher integer. The auto refresh
command must be followed by NOP’s until the auto refresh
operation is completed. All banks will be in the idle state at
the end of auto refresh operation. The auto refresh is the
PRELIMINARY
WE
WE
RAS
(min) requirement, performs precharge on all banks. At
RC
. The auto refresh command can only be asserted with
with high on A10/AP after both banks have satisfied
(min)”. The minimum number of clock cycles required
CS
(December, 2004, Version 0.0)
,
RAS
and
RC
CAS
” with clock cycle time and
with high on CKE and
CS
,
RAS
and
15
preferred refresh mode when the SDRAM is being used for
normal data transactions. The auto refresh cycle can be
performed once in 15.6us or a burst of 4096 auto refresh
cycles once in 64ms.
Self Refresh
The self refresh is another refresh mode available in the
SDRAM. The self refresh is the preferred refresh mode for
data retention and low power operation of SDRAM. In self
refresh mode, the SDRAM disables the internal clock and all
the input buffers except CKE. The refresh addressing and
timing is internally generated to reduce power consumption.
The self refresh mode is entered from all banks idle state by
asserting low on
being low matters, all the other inputs including clock are
ignored to remain in the self refresh.
The self refresh is exited by restarting the external clock and
then asserting high on CKE. This must be followed by NOP’s
for a minimum time of “t
state to begin normal operation. If the system uses burst auto
refresh during normal operation, it is recommended to used
burst 4096 auto refresh cycles immediately after exiting self
refresh.
WE . Once the self refresh mode is entered, only CKE state
CS
,
RAS
RC
AMIC Technology, Corp.
” before the SDRAM reaches idle
,
CAS
and CKE with high on
A43L1632